GB1126998A - Digital coder - Google Patents
Digital coderInfo
- Publication number
- GB1126998A GB1126998A GB23394/67A GB2339467A GB1126998A GB 1126998 A GB1126998 A GB 1126998A GB 23394/67 A GB23394/67 A GB 23394/67A GB 2339467 A GB2339467 A GB 2339467A GB 1126998 A GB1126998 A GB 1126998A
- Authority
- GB
- United Kingdom
- Prior art keywords
- flop
- flip
- charge
- condenser
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
1,126,998. Analogue to digital converters. INTERNATIONAL STANDARD ELECTRIC CORP. 19 May, 1967 [17 June, 1966], No. 23394/67. Heading G4H. In an analogue to digital converter a binary counter controls, through a decoder circuit and a plurality of current generators, the charge on the condenser which is compared with the signal voltage to obtain a signal when they are equal. The converter has a characteristic approximating to a logarithmic function, Fig. 3, Clock pulses H from source 40 are applied to a seven stage counter 10, Fig. 4. As the value in the counter increases a waveform is generated consisting of a series of straight line segments, the capacitor C being charged at a different rate to obtain each segment. Decoder 11 receiving the outputs from the three most significant stages of the counter gives a signal on one of eight leads P0-P7 connected via Or gates 12-15 to control one of the four current sources 16-19 to charge the capacitor at four different rates. The unknown signal is applied at BF and compared at 20 with the capacitor charge. At the beginning of the cycle the capacitor C is short-circuited by transistor T which is held conducting by a signal RAZ from flip-flop B7. At a count of 0000001, this flip-flop is reset and the condenser begins to charge at the lowest rate under the control of the signal on lead P0 and current source 16. At a count of 16 the condenser begins to charge at a higher rate, at 32 the rate increases again and so on to derive the curve of Fig. 3. When the condenser voltage equals the unknown voltage BF the comparator 20 gives an output which sets flip-flop 27, the next clock pulse H then causes flip-flop B9 to reset closing the gate 26. The last clock pulse H applied to store 30 causes the value then standing in the counter to be displayed. An automatic centring circuit is provided including flip-flop B7, B8, B9 and gate 22 and a time constant circuit 24. In coding speech signals, the samples will be half positive and half negative. Over an interval the most significant digit of the coded value will therefore be " 0 " and " 1 " an equal number of times. This digit is transferred via flip-flop B7 to flip-flop B8 and it applies a charge or discharge to a condenser in circuit 24 according to whether it is " 1 " or " 0 ". The value on the condenser is fed back to the comparator to shift the origin of the curve, Fig. 3, until the correct balance is achieved.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR65921A FR1493578A (en) | 1966-06-17 | 1966-06-17 | Analog to digital converter |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1126998A true GB1126998A (en) | 1968-09-11 |
Family
ID=8611192
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB23394/67A Expired GB1126998A (en) | 1966-06-17 | 1967-05-19 | Digital coder |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE699522A (en) |
CH (1) | CH457552A (en) |
ES (1) | ES341950A1 (en) |
FR (1) | FR1493578A (en) |
GB (1) | GB1126998A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2333299C3 (en) * | 1973-06-29 | 1979-04-26 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Circuit arrangement for converting analog signals into PCM signals and from PCM signals into analog signals |
FR2315199A1 (en) * | 1975-06-20 | 1977-01-14 | Thomson Csf | ENCODER WITH NORMALIZED COMPRESSION LAW FOR M.I.C. TYPE TELEPHONE TRANSMISSIONS |
-
1966
- 1966-06-17 FR FR65921A patent/FR1493578A/en not_active Expired
-
1967
- 1967-05-19 GB GB23394/67A patent/GB1126998A/en not_active Expired
- 1967-06-06 BE BE699522D patent/BE699522A/xx unknown
- 1967-06-13 CH CH835167A patent/CH457552A/en unknown
- 1967-06-17 ES ES341950A patent/ES341950A1/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR1493578A (en) | 1967-09-01 |
CH457552A (en) | 1968-06-15 |
ES341950A1 (en) | 1968-09-16 |
BE699522A (en) | 1967-12-06 |
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