GB1107047A - Improvements in or relating to a receiver for a multi-channel time division multiplex telecommunication system - Google Patents

Abstract

1,107,047. Multiplex pulse code signalling. GENERAL ELECTRIC CO. Ltd. 6 June. 1966 [4 June, 1965], No. 24013/65. Heading H4L. In a time division multiplex system in which the transmitted signal includes a regularly recurring pulse pattern forming a synchronizing signal controlling the channel distribution at the receiver, the receiver includes means for checking the timing of the channel distribution in relation to the synchronizing signal and providing an indication of synchronism or loss of synchronism at each check, and means for adjusting the timing of the channel distributer only after a predetermined number of successive indications of loss of synchronism. As described there are 24 channels per frame each channel consisting of 8 bits. 23 information channels are provided and the 24th channel carries the synchronizing signal, i.e. 00011011. The incoming signal is supplied via terminal 1 to a shift register 2 controlled by a bit-rate signal extracted from the incoming signal and supplied via terminal 3. The outputs of the shift register are connected in accordance with the synchronizing signal to an AND gate 4 which also receives as a reference signal a pulse at the frame frequency via AND gate 8 derived from the frequency dividers 7, 9 controlling the channel distribution. The bit-rate signal is supplied via terminal 5 and AND gate 6 to the frequency divider 7 which provides an output at the channel frequency, divider 9 providing an output in the digit eight position of channel twenty-four of each frame. Thus only when the receiver is synchronized will a pulse appear at the output of gate 4 and this inhibits gate 14 and via bi-stable circuit 15 enables AND gate 6. The pulses from divider 9 are also supplied via a delay 12 and differentiator 13 to the gate 14 so that if synchronism is lost a pulse will be supplied via INHIBIT gate 16 to set the bi-stable circuit 15 to remove the enabling input from gate 6 and block the pulses controlling divider 7. To prevent temporary errors in the received signal from initiating this operation the pulses from gates 4 and 14 are applied to a bi-stable device 17 so that when the receiver is synchronized an integrator 18 is charged and when an error occurs it is discharged. The arrangement is such that four successive error signals (four frames) are required for the integrator 18 output to fall to a sufficient level to trip a bi-stable device 21 and remove the inhibiting input from gate 16. The receiver will be stopped at its channel twentyfour digit eight position and the gate 8 will maintain its output reference pulse so that when the synchronizing pulse pattern appears again channel distribution will restart as soon as the integrator 18 has recharged to the required level.