GB1105628A - Simplified data-processing system - Google Patents

Abstract

1,105,628. Digital computers. INTERNATIONAL STANDARD ELECTRIC CORPORATION. 30 July, 1965 [31 July, 1964], No. 32748/65. Heading G4A. An electrical digital data processing system includes a plurality of logic units, each being adapted to perform a logical operation on either one or two words when enabled by enabling signals from a sequencing circuit and from the instruction being obeyed, each said logic unit being connected permanently to one or more registers according to the logical operation it performs, each said unit including a first set of conductors and a second set of conductors and decoupling elements arranged according to the operation to be carried out. As shown (Fig. 1), an electrical digital data processing system comprises a core-memory ME with decoder DC, address selector SA, single word memory register RM, single word accumulator register RT, an instruction register RO, RA, a programme counter CP, a plurality of logic units OP each permanently wired for performing a single elementary operation on the contents of one or two registers and a sequencing circuit DT for enabling logic units at predetermined, phases of a cycle of operation, said units being selected by the order part RO of the instruction register. A logic unit showing only those connections necessary for. comparing the settings of two registers A0 and A4 is illustrated in Fig. 5. For each bit position of the register a grid such as. ELO is provided consisting of horizontal wires to which pulses may be applied and vertical wires connected to the individual bi-stable elements of the registers. Resistors such as Re1 are provided in the horizontal wires and diodes such as di1 di2 at certain of the intersections. A common lead pc connects the horizontal wires by way of diodes di3 to the " set " terminal S of a binary counter A<SP>1</SP>40 of register A<SP>1</SP>4. Thus a pulse applied to the two wires ao will reach terminal S only if the bits in registers A00 and A40 are the same. During a first phase of an instruction execution, logic units are enabled whereby RM is zeroized and the value of the programme counter CP is transferred to the address part RA of the instruction register to control the reading in parallel of the next instruction from memory into register RM and from these into the previously cleared instruction register. During a second phase, the operand identified by the address in RA is read from memory into register RM. During a third phase; one or more logic units are selected in sequence to perform the required operation (as determined by the order code in RO) on RM or both RM and RT. Decoding of the order codes in RO causes one only of a number of wires f10 (Figs. 1 and 11) to be energized thereby opening a number of AND gates pt in a sequence determined by the sequencing circuit DT whereby logic units are enabled in such a sequence as to perform the required operation. A signal also passes along wire fl1 if the instruction being decoded involves indirect addressing, a further phase of operations (between phases one and two above) being included to cater for this. CB is a loop counter and RD is a spare register or registers which may be considered as forming part of memory ME and through which input/output data is transferred. Memory ME may comprise 16,384 words of 3 characters each. The characters each comprise 7 bits plus one for parity. Instructions comprise a one character order code and a two character address code. Cycle diagrams for the following instructions are given: add one, subtract one, compare, zeroize, invert, transfer to memory, transfer to other register.