GB1095293A - - Google Patents
Info
- Publication number
- GB1095293A GB1095293A GB1095293DA GB1095293A GB 1095293 A GB1095293 A GB 1095293A GB 1095293D A GB1095293D A GB 1095293DA GB 1095293 A GB1095293 A GB 1095293A
- Authority
- GB
- United Kingdom
- Prior art keywords
- pulse
- input
- capacitor
- point
- dec
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
1,095,293. Pulse shaping circuits. FUJITSU Ltd. Dec. 24, 1964 [Dec. 28, 1963], No. 52489/64. Heading H3P. A pulse shaping circuit initiates a steep fronted output pulse at a predetermined time after the peak of an input pulse having sloping leading and trailing edges. During the sloping leading edge 27a, Fig. 3a, of an input pulse, capacitor 32, Fig.2, charges via diode 36 to produce at point 34 a pulse with a rising edge 37Fig. 3b. Once the peak of the input signal is passed the capacitor 32 remains charged to the potential at point 29 until the input has dropped sufficiently for diode 35 to conduct, point 47, and discharge the capacitor. The resulting pulse, Fig. 3b, is then differentiated, Fig. 3c, and the negative going portion clipped to produce a steep fronted output pulse, 3d whose delay with respect to the input pulse may be controlled by potentiometer 28.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7108363 | 1963-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1095293A true GB1095293A (en) | 1967-12-13 |
Family
ID=13450262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1095293D Expired GB1095293A (en) | 1963-12-28 | 1964-12-24 |
Country Status (3)
| Country | Link |
|---|---|
| DE (1) | DE1293838B (en) |
| FR (1) | FR1419162A (en) |
| GB (1) | GB1095293A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2827959C3 (en) * | 1978-06-26 | 1981-01-22 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Circuit arrangement for evaluating the bell-shaped clock signals of different amplitudes emitted by a clock |
-
1964
- 1964-12-22 DE DE1964F0044785 patent/DE1293838B/en active Pending
- 1964-12-24 GB GB1095293D patent/GB1095293A/en not_active Expired
- 1964-12-28 FR FR62D patent/FR1419162A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR1419162A (en) | 1965-11-26 |
| DE1293838B (en) | 1969-04-30 |
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