GB1083317A - Static counters - Google Patents

Static counters

Info

Publication number
GB1083317A
GB1083317A GB1406265A GB1406265A GB1083317A GB 1083317 A GB1083317 A GB 1083317A GB 1406265 A GB1406265 A GB 1406265A GB 1406265 A GB1406265 A GB 1406265A GB 1083317 A GB1083317 A GB 1083317A
Authority
GB
United Kingdom
Prior art keywords
signals
auxiliary
store
gates
counting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1406265A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Licentia Patent Verwaltungs GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DEL43578A external-priority patent/DE1205147B/en
Priority claimed from DE1964L0047479 external-priority patent/DE1212151C2/en
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Publication of GB1083317A publication Critical patent/GB1083317A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers

Abstract

1,083,317. Electronic counters. LICENTIA PATENT-VERWALTUNGS-G.m.b.H. April 2, 1965 [April 3, 1964], No. 14062/65. Addition to 1,072,553. Heading G4A. A gated counter of the type described in the parent Specification in which each stage comprises a main store and an auxiliary store responding respectively to interlaced count and auxiliary count pulses t 1 , t 2 , is characterized in that the output signal from an auxiliary store changes its state in the middle of the output signal from its associated main store and again in the middle of the gap between successive output signals from the main store. The main stores S A and auxiliary stores H are controlled by OR-NOT gates V which are controlled by setting AND gates & s , & s 1 and holding AND gates & h , & h <SP>1</SP> in much the same manner as in the parent Specification except that signals H change state exactly in the middle of signals A and in the middle of the gap between two signals A. Embodiments are described for forward counting, backward counting, presetting, and decimal-coded binary counting, the logic circuits being adapted accordingly.
GB1406265A 1962-11-28 1965-04-02 Static counters Expired GB1083317A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DEL43578A DE1205147B (en) 1962-11-28 1962-11-28 Static counter
DEL47348A DE1212150B (en) 1962-11-28 1964-03-20 Static counter
DE1964L0047481 DE1212152C2 (en) 1962-11-28 1964-04-03 Static counter
DE1964L0047479 DE1212151C2 (en) 1964-04-03 1964-04-03 Static counter with main and auxiliary memory for each counter level

Publications (1)

Publication Number Publication Date
GB1083317A true GB1083317A (en) 1967-09-13

Family

ID=27437188

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1406265A Expired GB1083317A (en) 1962-11-28 1965-04-02 Static counters

Country Status (2)

Country Link
FR (1) FR92804E (en)
GB (1) GB1083317A (en)

Also Published As

Publication number Publication date
FR92804E (en) 1969-01-03

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