GB1082270A - Simplified data processing system - Google Patents

Abstract

1,082,270. Digital electric computers. INTERNATIONAL STANDARD ELECTRIC CORPORATION. Sept. 24, 1965 [Sept. 25, 1964], No. 40760/65. Heading G4A. A digital electric circuit for performing a comparison operation comprises a subtraction logic unit to note the presence of borrow belonging to the column of upper rank of two members being compared, and an exclusive OR logic unit to note the equality or inequality of both operands and in which means is provided for using the preceding results to determine whether one of the operands is greater than, equal to, or less than the other operand. In operation the operands are stored one in register RM, one in register RT (Fig. 1, not shown) and a comparison instruction is decoded in register RO (Figs. 1 and 6, not shown) to open the appropriate signal paths. As soon as the operands are in the registers the subtraction unit calculates the borrows for the various columns of the numbers, however only the column of uppermost rank is taken into account. If there is a borrow in this rank a signal A6b (Fig. 8, not shown) and two other enabling signals are applied to an AND gate, the signals allowing a bi-stable circuit to be set. In the absence of A6b the bi-stable circuit remains reset. The exclusive OR operation or sum modulo 2 is carried out and stored in register RM. If the operands are equal then RM stores zero, thus enabling signals #A20 to #A26 from the register RM to be supplied to an AND gate (Fig. 9, not shown). If the operands are equal then the AND gate is enabled to allow an affirmationnegation amplifier AN or alternatively a flipflop to originate an A2a signal. If any of the #A20 to #A26 signals is absent then an #A2a signal is produced. Two flip-flops D30, D31 are used to indicate the three conditions x>Y, y=Y, z<y. Thus signal #A2a and three enabling signals (Fig. 10, not shown) are applied to the set terminal of D31 to record the inequality of the operands. If at the same time D26 (absence of carry) plus an enabling signal is applied to the set terminal of D30 then x>y. If D30 exists (x#y) then with two enabling signals in time t0 an amplifier Ai is caused to deliver a signal b00 which causes a program counter to increase by one. If D31 and #D30 exist (x<y) with two enabling signals in the following time period t1 then Ai emits another signal b00 and the counter again advances. The program counter advances can be used to cause program jumps.