GB1067427A - Circuit arrangement for the parallel addition and subtraction of decimal digits - Google Patents

Circuit arrangement for the parallel addition and subtraction of decimal digits

Info

Publication number
GB1067427A
GB1067427A GB3388564A GB3388564A GB1067427A GB 1067427 A GB1067427 A GB 1067427A GB 3388564 A GB3388564 A GB 3388564A GB 3388564 A GB3388564 A GB 3388564A GB 1067427 A GB1067427 A GB 1067427A
Authority
GB
United Kingdom
Prior art keywords
stage
carry
subtraction
gate
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3388564A
Inventor
Walter Kasper
Hulmut Logisch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SOEMMERDA BUEROMASCHWERK
Original Assignee
SOEMMERDA BUEROMASCHWERK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SOEMMERDA BUEROMASCHWERK filed Critical SOEMMERDA BUEROMASCHWERK
Priority to GB3388564A priority Critical patent/GB1067427A/en
Publication of GB1067427A publication Critical patent/GB1067427A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Punching Or Piercing (AREA)
  • Control Of Conveyors (AREA)

Abstract

1,067,427. Electric calculating apparatus. BUROMASCHINENWERK SOMMERDA. VEB. Aug. 19, 1964, No. 33885/64. Heading G4A. In a parallel arrangement for the addition or subtraction of binary-coded decimal numbers, a first number is added to or subtracted from a second number contained in two-state stages A1-A4 of a register and the carries generated through " and " gates K6, K8, K10, K12 or K7, K9, K11, K13 to temporary carry storage two-state stages E2-E4 are transferred to the next stages of the register through " and " gates K2-K4. A decimal correction device KR controlled through "and" gate K15 and " or " gate D1 adds or subtracts through " and " gate K5 a " 6 " through carry stage E2 and accumulator stage A3 and simultaneously switches stage E for a carry to the next tetrad. The numbers are read out of and into a storage matrix and the signs are first read into stage A1 which triggers stage M previously set to addition or subtraction in order to control the ADD or SUB lines. The presence of a carry in E beyond the last decimal place indicates a negative number and recomplementing is achieved by a control trigger REK switched on by the control signal from a counter Z which recounts through the result AC to form O-AC whilst M is blocked.
GB3388564A 1964-08-19 1964-08-19 Circuit arrangement for the parallel addition and subtraction of decimal digits Expired GB1067427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB3388564A GB1067427A (en) 1964-08-19 1964-08-19 Circuit arrangement for the parallel addition and subtraction of decimal digits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3388564A GB1067427A (en) 1964-08-19 1964-08-19 Circuit arrangement for the parallel addition and subtraction of decimal digits

Publications (1)

Publication Number Publication Date
GB1067427A true GB1067427A (en) 1967-05-03

Family

ID=10358715

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3388564A Expired GB1067427A (en) 1964-08-19 1964-08-19 Circuit arrangement for the parallel addition and subtraction of decimal digits

Country Status (1)

Country Link
GB (1) GB1067427A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103970503A (en) * 2013-01-28 2014-08-06 三星电子株式会社 Adder capable of supporting addition and subtraction and method of supporting addition and subtraction

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103970503A (en) * 2013-01-28 2014-08-06 三星电子株式会社 Adder capable of supporting addition and subtraction and method of supporting addition and subtraction
CN103970503B (en) * 2013-01-28 2019-03-01 三星电子株式会社 The method that can be supported the adder of addition and subtraction and support addition and subtraction

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