GB1055889A - Improvements in or relating to apparatus for processing data - Google Patents

Abstract

1,055,889. Digital computers. COMPAGNIE DES MACHINES BULL. Dec. 2, 1963 [Dec. 5, 1962], No. 47519/63. Heading G4A. Data read-out of store 1 is stored in three registers, 2A, 2B, 2C constituting the first register, 3 the second register and 4 the third. The data in 2A, 2B, 2C can be transferred to address register 7A, 7B, 7C either directly through gates 13-15 or indirectly through gates 16-18, intermediate register 8A, 8B, 8C and gates 19-21. The instruction part of the read out data, in register 3, is decoded at 22 to energize one of a number of output lines 23, and a further pair of bits in register 4 controls the energization of one of four outputs S0-S3. The signals so generated control the next address from which a data word is to be read; this can be the number in 2A-2C or an address inserted at 31-33. The arrangement is described as carrying out arithmetic operations (addition) on two numbers each of two binarycoded decimal digits, the pair of lower-order digits being used to select the sum and carry digits from the appropriate address in store 1, part of which is thus used as a decimal digit addition table from which sum and carry digits are read, register 2C (a one-bit register) being used for the carry. The operation is described with the aid of a table giving the instruction codes used and illustrating the flow of information as the addition proceeds.