GB1050470A - - Google Patents

Abstract

1,050,470. Digital data storage. STANDARD TELEPHONES & CABLES Ltd. Nov. 8, 1963 [Nov. 9, 1962], No. 44167/63. Heading G4C. In an arrangement for selecting an empty compartment in a data storage device, the compartments are scanned sequentially to determine if they are free or occupied, the number of a free compartment being transferred to a first register and thence to a second register if the second register is empty but to the next free compartment found by the scanner if the second register is occupied, the second register supplying the number of an empty compartment in response to an external request, the number of another free register being transferred from the empty compartment to the second register. The arrangement is applicable in a controlling memory as used in an automatic telephone exchange such as is described in Specification 963,329 [Division H4] and comprises a first register RA a second register RB and a five row ferrite core memory MC, each row constituting a " compartment " which can store data relating to a telephone call. A circuit DA controls sequential scanning of the five memory rows during timing cycles T1-T5, Fig. 2. During time T1 the contents of row 1 is read out to a logical circuit CL and, assuming the matrix memory and registers to be initially empty, a " 0 " (which is not a row number) is transferred from the register RA to row 1, a " 1 " representing row 1 is supplied by the logical circuit CL, via register RA which is reset to " 0," to register RB. During time T2, row 2 is scanned and, since it is empty, " 2 " is registered in RA, and the " 0 " from register RA is stored in row 2. During time T3, row 3 is scanned and, since it is empty, " 3 " is registered in RA, the " 2 " therefrom being registered in row 3 of the matrix. During times T4, T5, free row numbers " 3 " and " 4 " respectively are registered in rows 4 and 5. During time T6, row 1 is scanned again, free row number " 5 " is transferred from RA to row 1 and free row number " 1" from the logical circuit CL to register RA. A comparator CC which continuously compares the contents of registers RA, RB detects equality and erases the " 1 " from RA. Thus each free row, except row 2 contains the number of the previous free row, the number " 1 " of the first free row being in register RB. Assuming now that marker circuit MQ requests a free row at time T6/t2; the free row number from register RB is transmitted via a lead pr to the logic circuit CL which sets the matrix row scanner EX to that row, the row number " 5 " of the next free row being read out from row 1 to the register RB. In response to subsequent requests, rows 5, 4, 3, 2 are seized in a similar way, but when row 3 is seized the comparator CC, detecting a " 3 " in both registers RA and RB, causes register RA to be set to " 0." From time T10 onwards all the rows, unless released, are busy and both registers RA and RB store " 0."