GB1048525A - Data processing system - Google Patents

Abstract

1,048,525. Computer input/output. INTERNATIONAL BUSINESS MACHINES CORPORATION. July 16, 1965, No. 30236/65. Heading G4A. A data processing system comprises means to transfer blocks of data between a memory and one or more input/output (I/O) devices via a plurality of buffer registers, an indicator which is set when two transfer operations cause data from a second block to enter the buffer registers before all the data in a previous block has left them, and means responsive to the setting of the indicator to store information identifying the data of the first block still in the buffer registers. A plurality of input/output channels, each as above, are provided. A START I/O programmed instruction specifies, besides the channel and device numbers, the address of a first channel command word (CCW). The CCW, originally specified by the programme, has fields indicating the operation (i.e. input or output), the first memory address to receive or deliver part of the block of data to be transferred (" data address " field), a count field initially indicating the number of bytes in the block, and flags including one to indicate if data chaining is required (see below). The address of the first CCW is placed in a " current CCW address " field of a unit control word (UCW) associated with the particular I/O device concerned. The UCW also receives the data address field, count field and flags from the CCW. The I/O operation now takes place with incrementing of the data address field and decrementing of the count field, and after it has finished, an interrupt occurs and a channel status word (CSW) storing the device address also receives the final value of the count, the current CCW address field incremented by 8 (there being 8 bytes to a word) and device status bits, all from the UCW, the status bits having been previously stored in the UCW. The I/O operation may be terminated by the I/O device before the count has reached zero. For each channel, five buffer registers in series are provided, together with a five-stage register which stores a marker bit in the stage corresponding to the buffer register holding the last byte provided under control of the current CCW. If the I/O operation is terminated by the I/O device, the number of bytes still in the buffer registers is determined by shifting the data and marker bits from the registers and counting the number of shifts required to move the marker bit from its register. This number is added to the count field in the UCW before the CSW is assembled and stored. One I/O operation may be controlled by a series of CCW's in turn (" data chaining "), a CSW being assembled only after the final CCW has been used. In this case the above procedure in the case of termination by the I/O device, is modified as follows. A chaining boundary latch is set when the last byte defined by a CCW enters the buffer registers and reset when that byte leaves the registers. The UCW also stores the address of the preceding CCW. The number of shifts required to move the marker bit from its register is determined on termination as before but the number is added to the count field from the preceding or the current CCW depending on whether the chaining boundary latch is set or not. Also when the boundary latch is set, the CSW receives the preceding CCW address incremented by eight rather than the current CCW incremented by eight. The incrementing by eight just referred to assumes that the next CCW is stored in the next memory word from the present CCW. If this is not so, a programmed TRANSFER IN CHANNEL command must be provided to indicate the address of the next CCW. The system is microprogramme-controlled, a read-only store as in Specification 985,347, which is referred to, being used.