GB1037872A - Blocking oscillator circuit - Google Patents

Abstract

1,037,872. Transistor blocking oscillator circuits; circuits employing bi-stable magnetic elements. STANDARD TELEPHONES & CABLES Ltd. June 28, 1963, No. 25783/63. Headings H3B and H3T. A blocking oscillator has three or more squareloop core feedback transformers. The oscillator may be arranged so that the switching of the cores takes place together or successively. Fig. 1 shows a transistor blocking oscillator having a series of feedback transformers with successively increasing number of primary turns. In response to a triggering pulse the transistor saturates and the current rises to a value determined by the winding with the largest number of turns. In due course its core will saturate and the feedback will cease but conduction is momentarily maintained by stored charge carriers. The current rises and the next core starts to switch. Thus the cores switch in succession and a step-wise increase in transistor current occurs until the final core switches. They are then simultaneously reset by a steady current or pulse of current in the reset windings np. Output pulses occur in succession in windings no. Instead of grading the number of primary turns the secondary or bias winding turns or the bias currents may be graded (Figs. 4 and 5, not shown). Resetting may be effected successively by a second transistor connected in push-pull relationship to the first (Fig. 6, not shown). The output windings may be connected to polarity selection diodes so that output pulses are provided by the windings in succession throughout set and reset periods. Output windings may be arranged in series so that a train of pulses is produced (Fig. 7, not shown). The push-pull circuit may be free running or, by the provision of a differentiating transformer, a neutralizing pulse may be fed back to terminate operation after each " set " cycle and after each " reset " cycle or after each cycle of " set " and " reset " (as explained with reference to Figs. 3-11 (not shown) and as illustrated in Fig. 12, not shown). Resetting may alternatively be effected by transistor feedback circuits individual to each core in which case, if the output diodes conduct only during the resetting period delayed output pulses of different widths are available in different output windings (Figs. 12 and 13, not shown). Triggering may be effected by pulses applied to the emitter or base via A.C. or D.C. couplings or through a core winding (Figs. 14-18, not shown). Variation of the " set " and " reset " duration may be effected by varying directly, or through variable resistors, the base, collector or reset winding current (Figs. 5 and 14-18, not shown).