GB1023960A - Phase slope delay network - Google Patents
Phase slope delay networkInfo
- Publication number
- GB1023960A GB1023960A GB617265A GB617265A GB1023960A GB 1023960 A GB1023960 A GB 1023960A GB 617265 A GB617265 A GB 617265A GB 617265 A GB617265 A GB 617265A GB 1023960 A GB1023960 A GB 1023960A
- Authority
- GB
- United Kingdom
- Prior art keywords
- phase
- frequency
- sine
- cosine
- tap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/0009—Time-delay networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/18—Networks for phase shifting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Networks Using Active Elements (AREA)
Abstract
1,023,960. Phase delay network. STANDARD TELEPHONES & CABLES Ltd. Feb. 12, 1965 [Feb. 13, 1964], No. 6172/65. Heading H3U. A circuit for delaying an incident signal comprises means for slicing the frequency spectrum of the signal into a plurality of bands; means coupled to said slicing means for adding a phase shift to each band proportional to the centre frequency thereof; and means coupled to said adding means for combining the phase shifted bands and producing a delayed replica of the signal. Fig. 3a shows an LCR iterative network to produce four band slicing having cross-over frequencies F 1 , F 2 , F 3 , Fig. 3b. In this network L 11 C 12 > L 1 C 2 >L 21 C 21 and e 11 +e 12 +e 21 +e 22 =e in at all frequencies. In Fig. 5 the incident signal to be delayed is applied to an all-pass filter bank 51 composed as in Fig. 3a but extended by iteration. The output of each filter, e.g. the filter having a centre frequency Fr, is fed to an R-C phase shifter network 52r having two outputs separated in phase leg 90 degrees, the two outputs corresponding to the sine and cosine of the frequency Fr and being fed tobalanced modulators 53r, 54r. The other inputs of the modulators are D.C. voltages proportional to the sine and cosine of a variable phase angle α; this angle a when plotted against the frequency to which it is applied must give a substantially linear function, the slope of which is dependent upon the desired delay. The sine and cosine D.C. voltages are obtained from balanced modulators 56r, 57r whose inputs are the voltage from the voltage controlled oscillator 58 and a voltage from a tap on the delay line 59 fed by the same V.C.O. Since the delay line has a tap corresponding to each set of associated balanced modulators and each tap along the line introduces greater delay the application of the resultant modulator outputs to the filter derived frequencies fed to the other group of modulators, e.g. 53r, 54r, produces the linear function sought. Thus, the output of the first tap on the delay line 59 produces the D.C. sine and cosine voltages for the lowest signal frequency band, the second tap the sine and cosine voltages for the second lowest band, and so on. The variation in the slope of phase vs. frequency, and hence the overall delay is produced by varying the control voltage of VCO 58. The delayed signal is produced by a summing amplifier 55.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US344621A US3293552A (en) | 1964-02-13 | 1964-02-13 | Phase slope delay |
US350908A US3324251A (en) | 1964-03-10 | 1964-03-10 | Electronically variable delay |
US434569A US3324397A (en) | 1965-02-23 | 1965-02-23 | Variable delay system having a plurality of successive delay sections each of a value one-half that of the preceding section |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1023960A true GB1023960A (en) | 1966-03-30 |
Family
ID=27407637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB617265A Expired GB1023960A (en) | 1964-02-13 | 1965-02-12 | Phase slope delay network |
Country Status (4)
Country | Link |
---|---|
BE (2) | BE659623A (en) |
GB (1) | GB1023960A (en) |
NL (2) | NL6501743A (en) |
SE (1) | SE305241B (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003107528A2 (en) * | 2002-06-18 | 2003-12-24 | Automotive Distance Control Systems Gmbh | Circuit arrangement for generating an iq signal |
US7274922B2 (en) | 2002-06-18 | 2007-09-25 | A.D.C. Automotive Distance Control Systems Gmbh | Circuit arrangement for generating an IQ-signal |
US7444365B2 (en) | 2002-06-18 | 2008-10-28 | A.D.C. Automotive Distance Control Systems Gmbh | Non-linear digital rank filtering of input signal values |
-
1965
- 1965-02-11 SE SE174465A patent/SE305241B/xx unknown
- 1965-02-12 BE BE659623D patent/BE659623A/xx unknown
- 1965-02-12 GB GB617265A patent/GB1023960A/en not_active Expired
- 1965-02-12 NL NL6501743A patent/NL6501743A/xx unknown
- 1965-03-17 NL NL6503421A patent/NL6503421A/xx unknown
- 1965-03-19 BE BE661338D patent/BE661338A/xx unknown
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003107528A2 (en) * | 2002-06-18 | 2003-12-24 | Automotive Distance Control Systems Gmbh | Circuit arrangement for generating an iq signal |
WO2003107528A3 (en) * | 2002-06-18 | 2005-01-13 | Adc Automotive Dist Control | Circuit arrangement for generating an iq signal |
US7274922B2 (en) | 2002-06-18 | 2007-09-25 | A.D.C. Automotive Distance Control Systems Gmbh | Circuit arrangement for generating an IQ-signal |
US7444365B2 (en) | 2002-06-18 | 2008-10-28 | A.D.C. Automotive Distance Control Systems Gmbh | Non-linear digital rank filtering of input signal values |
US7463181B2 (en) | 2002-06-18 | 2008-12-09 | A.D.C. Automotive Distance Control Systems Gmbh | Method of suppressing interferences in systems for detecting objects |
Also Published As
Publication number | Publication date |
---|---|
BE661338A (en) | 1965-09-20 |
BE659623A (en) | 1965-08-12 |
NL6501743A (en) | 1965-08-16 |
SE305241B (en) | 1968-10-21 |
NL6503421A (en) | 1965-09-13 |
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