GB1015341A - Improvements in or relating to pulse source fault detection circuits - Google Patents

Abstract

1,015,341. Pulse circuits. AUTOMATIC TELEPHONE & ELECTRIC CO. Ltd. June 18, 1964 [June 18, 1963], No. 24130/63. Heading H3T. In a circuit for detection of the absence of one or more clock pulses, each pulse is used to set a bi-stable device T1 which is reset by the same pulse after a delay imposed by DL, a second delayed pulse being provided, occurring after the next pulse is due, an indication being given signifying the absence of the next pulse if the bi-stable device is still in the " reset " state at the time of the second delayed pulse. As described, 1 Ás. clock pulses at OL, occurring at 10 Ás. intervals are amplified by inverters I1, I2 and fed to a correctly terminated delay line DL which supplies pulses delayed by slightly more than 10Ás. to an emitter follower E2 and inverter 14 and pulses delayed by 5Ás. to an emitter follower E1 and inverters 13, I5. Each pulse at OL sets the transistorized bistable device T1 which is reset by the first delayed pulse. In the absence of the next pulse at OL, T1 remains in its reset state, opening an AND gate G2 which allows the second delayed pulse to set the bi-stable device T2 which provides a fault indication. The operation may be inhibited at SP and restored at RT. Delay line DL may be replaced by monostable devices.