GB1010585A - Circuit arrangement for carrying out multiplication and rounding-off operations - Google Patents

Abstract

1,010,585. Electric digital multipliers. BUROMASCHINENWERK SOMMERDA VEB. July 29, 1964, No. 30087/64. Heading G4A. In a multiplication circuit in which the multiplicand is added into the partial product under the control of successive multiplier digits commencing with the most significant, means are provided for inserting a mark symbol to indicate the least significant digit of the multiplier and a further mark symbol to indicate the most significant digit to be deleted from the product in a rounding-off operation. Initially the multiplier is entered in a register 1, Fig. 3, and the mutiplicand in a register 2, the lower order digits of the partial product being accumulated in a register 3, the higher order digits being transferred to the multiplier register 1 as the multiplier digits are successively processed. The three registers 1, 2, 3 are arranged as shown to form a matrix, the matrix elements being magnetic cores and the numbers in the calculation being coded in binary-decimal code and processed in serial-parallel form. The twelve matrix columns, corresponding to eleven decimal digits plus a sign digit are scanned by lines S1-S12 which are energized via a recoder 4 from the outputs Z1 Z2, Z4, Z8 of a 4-stage binary control counter Z (Fig. 2, not shown). In the multiplication operation, the first step is the multiplication of the sign digits of the multiplier and multiplicand, the result sign digit being entered in registers 1 and 2. In the second step, a mark symbol " 1100 " is written into column position S12 of register 3. In the third step, the contents of the register 1 is recycled, the highest order digit, in column S12, being sensed to determine whether it is zero or not. If this digit is not zero, the multiplicand is added to the partial product in an adder (Fig. 1, not shown) and the multiplicand digit is reduced by unity. If this digit is zero, the multiplier and partial product is register 1 and 3 are shifted by one place to the left. The multiplication operation is terminated when the mark " 1100 " is sensed in column S12 of row 1. To effect the rounding off, the control counter Z is set to a value corresponding to the highest order position in row 3 (which contain the lower order digits of the product) to be cut off, a mark in the form of " 11" " in the two highest of the four bit positions being written in this position, the highest remaining digit being increased by unity by adding five to the digit to be cut off if the cut-off digit was five or greater. The product is left shifted, the registers 1, 3 operating as a double length register, until the mark reaches column S12 of register 3, when the shift is terminated, the product of the desired length now being stored in the register 1.