GB1009811A - Semiconductor structures - Google Patents

Semiconductor structures

Info

Publication number
GB1009811A
GB1009811A GB5128463A GB5128463A GB1009811A GB 1009811 A GB1009811 A GB 1009811A GB 5128463 A GB5128463 A GB 5128463A GB 5128463 A GB5128463 A GB 5128463A GB 1009811 A GB1009811 A GB 1009811A
Authority
GB
United Kingdom
Prior art keywords
layer
wafer
region
emitter
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5128463A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CBS Corp
Original Assignee
Westinghouse Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Westinghouse Electric Corp filed Critical Westinghouse Electric Corp
Publication of GB1009811A publication Critical patent/GB1009811A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)

Abstract

1,009,811. Semi-conductor devices. WESTINGHOUSE ELECTRIC CORPORATION. Dec. 31, 1963, No. 51284/63. Heading H1K. An ohmic contact is made to a diffused layer of one conductivity type in a region of the opposite conductivity type by depositing an epitaxial layer on the diffused layer and fusing an ohmic contact to the epitaxial layer. As shown, Fig. 7, an NPNP switching device is manufactured by diffusing indium, gallium, aluminium, or boron into the surface of a circular N-type silicon wafer to produce P-type surface regions 17, 18. The top surface of the wafer is oxidized and a photolithographic technique is used to produce a mask through which antimony, arsenic, or phosphorus is diffused to produce the annular emitter region 28. The remaining oxide layer is removed and an epitaxial layer 36 of degenerate N-type silicon is deposited over the entire top surface of the wafer by decomposition of silicon tetrachloride and a chloride or other halide of the doping material carried in a hydrogen stream. The sides of the emitter region are then isolated from the surrounding regions by etching annular grooves 40, 42. The epitazial layer and part of the surface of the gate region 17 are also removed by etching and ohmic contacts are produced by alloying a foil 48 of gold containing antimony, arsenic or phosphorus to the epitazial layer convering the emitter region, and alloying foils 52, 54 of gold containing boron, aluminium, gallium or indium to the exposed surface 43 of region 17 and to the underside of the wafer respectively. In a second embodiment, Fig. 10, the diffused regions 17, 18, and 28 are produced as in the first embodiment, an oxide layer 60 is formed over the entire surface of the wafer, an annular window is etched in the layer to expose the emitter region 28 and a degenerate N-type silicon epitaxial layer 62 is deposited on top of the oxide layer so that it makes contact with the emitter region 28 through the window. A window is etched in the epitaxial and oxide layers 62, 60 to expose the gate region within the emitter ring, and the oxide layer is also removed from the lower face of the wafer. Ohmic contacts 64, 68, 70 are made to the emitter, gate, and collector electrodes by alloying doped gold foils to the wafer. The original wafer may be a slice of single crystal or dendritic crystal material. Specifications 889,058 and 913,674 are referred to.
GB5128463A 1963-01-25 1963-12-31 Semiconductor structures Expired GB1009811A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US25381863A 1963-01-25 1963-01-25

Publications (1)

Publication Number Publication Date
GB1009811A true GB1009811A (en) 1965-11-10

Family

ID=22961829

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5128463A Expired GB1009811A (en) 1963-01-25 1963-12-31 Semiconductor structures

Country Status (4)

Country Link
BE (1) BE642969A (en)
CH (1) CH416841A (en)
DE (1) DE1439959B2 (en)
GB (1) GB1009811A (en)

Also Published As

Publication number Publication date
DE1439959A1 (en) 1968-12-19
BE642969A (en) 1964-05-15
DE1439959B2 (en) 1971-05-06
CH416841A (en) 1966-07-15

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