GB0915218D0 - Clock device - Google Patents
Clock deviceInfo
- Publication number
- GB0915218D0 GB0915218D0 GBGB0915218.2A GB0915218A GB0915218D0 GB 0915218 D0 GB0915218 D0 GB 0915218D0 GB 0915218 A GB0915218 A GB 0915218A GB 0915218 D0 GB0915218 D0 GB 0915218D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- clock device
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0915218.2A GB0915218D0 (en) | 2009-09-02 | 2009-09-02 | Clock device |
| PCT/GB2010/051444 WO2011027155A1 (en) | 2009-09-02 | 2010-09-02 | Pll/dll clock generating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0915218.2A GB0915218D0 (en) | 2009-09-02 | 2009-09-02 | Clock device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB0915218D0 true GB0915218D0 (en) | 2009-10-07 |
Family
ID=41202989
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GBGB0915218.2A Ceased GB0915218D0 (en) | 2009-09-02 | 2009-09-02 | Clock device |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB0915218D0 (en) |
| WO (1) | WO2011027155A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1168559A (en) * | 1997-08-20 | 1999-03-09 | Nec Corp | Phase-locked loop circuit |
| US6181209B1 (en) * | 1998-12-04 | 2001-01-30 | Winbond Electronics Corp. | All-digital frequency following system |
| US6995590B1 (en) * | 2003-09-22 | 2006-02-07 | Altera Corporation | Hybrid phase/delay locked loop circuits and methods |
| US6982579B2 (en) | 2003-12-11 | 2006-01-03 | Micron Technology, Inc. | Digital frequency-multiplying DLLs |
| KR20060072459A (en) * | 2004-12-23 | 2006-06-28 | 삼성전자주식회사 | Phase locked loop device with variable load capacitor depending on frequency |
-
2009
- 2009-09-02 GB GBGB0915218.2A patent/GB0915218D0/en not_active Ceased
-
2010
- 2010-09-02 WO PCT/GB2010/051444 patent/WO2011027155A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011027155A1 (en) | 2011-03-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AT | Applications terminated before publication under section 16(1) |