GB0822458D0 - Store grouping - Google Patents
Store groupingInfo
- Publication number
- GB0822458D0 GB0822458D0 GBGB0822458.6A GB0822458A GB0822458D0 GB 0822458 D0 GB0822458 D0 GB 0822458D0 GB 0822458 A GB0822458 A GB 0822458A GB 0822458 D0 GB0822458 D0 GB 0822458D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- store grouping
- grouping
- store
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08100461 | 2008-01-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0822458D0 true GB0822458D0 (en) | 2009-01-14 |
GB2456621A GB2456621A (en) | 2009-07-22 |
GB2456621B GB2456621B (en) | 2012-05-02 |
Family
ID=40289746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0822458.6A Active GB2456621B (en) | 2008-01-15 | 2008-12-10 | Store grouping |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2456621B (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10579387B2 (en) | 2017-10-06 | 2020-03-03 | International Business Machines Corporation | Efficient store-forwarding with partitioned FIFO store-reorder queue in out-of-order processor |
US10606591B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
US10394558B2 (en) | 2017-10-06 | 2019-08-27 | International Business Machines Corporation | Executing load-store operations without address translation hardware per load-store unit port |
US11175924B2 (en) | 2017-10-06 | 2021-11-16 | International Business Machines Corporation | Load-store unit with partitioned reorder queues with single cam port |
US10417002B2 (en) | 2017-10-06 | 2019-09-17 | International Business Machines Corporation | Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses |
US10606590B2 (en) | 2017-10-06 | 2020-03-31 | International Business Machines Corporation | Effective address based load store unit in out of order processors |
US10572256B2 (en) | 2017-10-06 | 2020-02-25 | International Business Machines Corporation | Handling effective address synonyms in a load-store unit that operates without address translation |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6163821A (en) * | 1998-12-18 | 2000-12-19 | Compaq Computer Corporation | Method and apparatus for balancing load vs. store access to a primary data cache |
EP1050807A1 (en) * | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Memory access in a computer memory |
US6801982B2 (en) * | 2002-01-24 | 2004-10-05 | International Business Machines Corporation | Read prediction algorithm to provide low latency reads with SDRAM cache |
US20080162799A1 (en) * | 2006-12-28 | 2008-07-03 | Bryan Spry | Mechanism for write optimization to a memory device |
-
2008
- 2008-12-10 GB GB0822458.6A patent/GB2456621B/en active Active
Also Published As
Publication number | Publication date |
---|---|
GB2456621B (en) | 2012-05-02 |
GB2456621A (en) | 2009-07-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 20130107 |