GB0822115D0 - Out of order execution of floating point loads with integrated refresh mechanism - Google Patents

Out of order execution of floating point loads with integrated refresh mechanism

Info

Publication number
GB0822115D0
GB0822115D0 GBGB0822115.2A GB0822115A GB0822115D0 GB 0822115 D0 GB0822115 D0 GB 0822115D0 GB 0822115 A GB0822115 A GB 0822115A GB 0822115 D0 GB0822115 D0 GB 0822115D0
Authority
GB
United Kingdom
Prior art keywords
floating point
order execution
point loads
refresh mechanism
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0822115.2A
Other versions
GB2454816A (en
GB2454816B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB0822115D0 publication Critical patent/GB0822115D0/en
Publication of GB2454816A publication Critical patent/GB2454816A/en
Application granted granted Critical
Publication of GB2454816B publication Critical patent/GB2454816B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
GB0822115.2A 2008-01-15 2008-12-04 Out of order execution of floating point loads with integrated refresh mechanism Active GB2454816B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08100459 2008-01-15

Publications (3)

Publication Number Publication Date
GB0822115D0 true GB0822115D0 (en) 2009-01-07
GB2454816A GB2454816A (en) 2009-05-20
GB2454816B GB2454816B (en) 2012-02-22

Family

ID=40262631

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0822115.2A Active GB2454816B (en) 2008-01-15 2008-12-04 Out of order execution of floating point loads with integrated refresh mechanism

Country Status (1)

Country Link
GB (1) GB2454816B (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5951676A (en) * 1997-07-30 1999-09-14 Integrated Device Technology, Inc. Apparatus and method for direct loading of offset register during pointer load operation
US7188234B2 (en) * 2001-12-12 2007-03-06 Intel Corporation Run-ahead program execution with value prediction

Also Published As

Publication number Publication date
GB2454816A (en) 2009-05-20
GB2454816B (en) 2012-02-22

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20130107