GB0322242D0 - Method and apparatus for testing timing constraints - Google Patents

Method and apparatus for testing timing constraints

Info

Publication number
GB0322242D0
GB0322242D0 GB0322242A GB0322242A GB0322242D0 GB 0322242 D0 GB0322242 D0 GB 0322242D0 GB 0322242 A GB0322242 A GB 0322242A GB 0322242 A GB0322242 A GB 0322242A GB 0322242 D0 GB0322242 D0 GB 0322242D0
Authority
GB
United Kingdom
Prior art keywords
timing constraints
testing timing
testing
constraints
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0322242A
Other versions
GB2406400A (en
GB2406400B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to GB0322242A priority Critical patent/GB2406400B/en
Publication of GB0322242D0 publication Critical patent/GB0322242D0/en
Publication of GB2406400A publication Critical patent/GB2406400A/en
Application granted granted Critical
Publication of GB2406400B publication Critical patent/GB2406400B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
GB0322242A 2003-09-23 2003-09-23 Method and apparatus for testing timing constraints Expired - Fee Related GB2406400B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0322242A GB2406400B (en) 2003-09-23 2003-09-23 Method and apparatus for testing timing constraints

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0322242A GB2406400B (en) 2003-09-23 2003-09-23 Method and apparatus for testing timing constraints

Publications (3)

Publication Number Publication Date
GB0322242D0 true GB0322242D0 (en) 2003-10-22
GB2406400A GB2406400A (en) 2005-03-30
GB2406400B GB2406400B (en) 2005-11-30

Family

ID=29266498

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0322242A Expired - Fee Related GB2406400B (en) 2003-09-23 2003-09-23 Method and apparatus for testing timing constraints

Country Status (1)

Country Link
GB (1) GB2406400B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7526745B2 (en) 2004-12-08 2009-04-28 Telefonaktiebolaget L M Ericsson (Publ) Method for specification and integration of reusable IP constraints
US7447966B2 (en) * 2005-01-05 2008-11-04 Hewlett-Packard Development Company Hardware verification scripting

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517658A (en) * 1990-11-09 1996-05-14 Lsi Logic Corporation Method for testing design timing parameters using a timing shell generator
US5751596A (en) * 1995-07-27 1998-05-12 Vlsi Technology, Inc. Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system
US5751593A (en) * 1996-04-10 1998-05-12 Motorola, Inc. Accurate delay prediction based on multi-model analysis
US5819072A (en) * 1996-06-27 1998-10-06 Unisys Corporation Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints
US6086621A (en) * 1998-05-12 2000-07-11 Vsli Technology, Inc. Logic synthesis constraints allocation automating the concurrent engineering flows
GB2365155A (en) * 2000-07-24 2002-02-13 Motorola Inc Generation of test scripts from a system specification model
GB2377515A (en) * 2001-07-09 2003-01-15 Motorola Inc Test Specifications for System Specifications

Also Published As

Publication number Publication date
GB2406400A (en) 2005-03-30
GB2406400B (en) 2005-11-30

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20070923