GB0225252D0 - Semiconductor memory device having altered clock frequency for address and/or command signals,and memory module and system having the same - Google Patents
Semiconductor memory device having altered clock frequency for address and/or command signals,and memory module and system having the sameInfo
- Publication number
- GB0225252D0 GB0225252D0 GBGB0225252.6A GB0225252A GB0225252D0 GB 0225252 D0 GB0225252 D0 GB 0225252D0 GB 0225252 A GB0225252 A GB 0225252A GB 0225252 D0 GB0225252 D0 GB 0225252D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- address
- same
- clock frequency
- command signals
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20000052377 | 2000-09-05 | ||
KR10-2000-0079186A KR100396885B1 (en) | 2000-09-05 | 2000-12-20 | Semiconductor memory device lowering high frequency system clock signal for the use of operation frequency of address and command and receiving different frequency clock signals, memory module and system having the same |
GB0120457A GB2370667B (en) | 2000-09-05 | 2001-08-22 | Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0225252D0 true GB0225252D0 (en) | 2002-12-11 |
GB2379544A GB2379544A (en) | 2003-03-12 |
GB2379544B GB2379544B (en) | 2003-09-10 |
Family
ID=27256263
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0225251A Expired - Fee Related GB2379543B (en) | 2000-09-05 | 2001-08-22 | System comprising memory module |
GB0225252A Expired - Fee Related GB2379544B (en) | 2000-09-05 | 2001-08-22 | System comprising memory module |
GB0225250A Expired - Fee Related GB2379542B (en) | 2000-09-05 | 2001-08-22 | System comprising memory module |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0225251A Expired - Fee Related GB2379543B (en) | 2000-09-05 | 2001-08-22 | System comprising memory module |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0225250A Expired - Fee Related GB2379542B (en) | 2000-09-05 | 2001-08-22 | System comprising memory module |
Country Status (1)
Country | Link |
---|---|
GB (3) | GB2379543B (en) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA1243138A (en) * | 1984-03-09 | 1988-10-11 | Masahiro Kodama | High speed memory access circuit of crt display unit |
GB2177825B (en) * | 1985-07-12 | 1989-07-26 | Anamartic Ltd | Control system for chained circuit modules |
KR100252048B1 (en) * | 1997-11-18 | 2000-05-01 | 윤종용 | Data masking circuit and its method for semiconductor memory device |
KR100335504B1 (en) * | 2000-06-30 | 2002-05-09 | 윤종용 | 2 Channel memory system having shared control and address bus and memory modules used therein |
-
2001
- 2001-08-22 GB GB0225251A patent/GB2379543B/en not_active Expired - Fee Related
- 2001-08-22 GB GB0225252A patent/GB2379544B/en not_active Expired - Fee Related
- 2001-08-22 GB GB0225250A patent/GB2379542B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2379543A (en) | 2003-03-12 |
GB2379542A (en) | 2003-03-12 |
GB0225251D0 (en) | 2002-12-11 |
GB2379544B (en) | 2003-09-10 |
GB2379544A (en) | 2003-03-12 |
GB2379543B (en) | 2003-09-10 |
GB0225250D0 (en) | 2002-12-11 |
GB2379542B (en) | 2003-09-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20140822 |