GB0121585D0 - Multiplexing test pins on an ASIC - Google Patents

Multiplexing test pins on an ASIC

Info

Publication number
GB0121585D0
GB0121585D0 GB0121585A GB0121585A GB0121585D0 GB 0121585 D0 GB0121585 D0 GB 0121585D0 GB 0121585 A GB0121585 A GB 0121585A GB 0121585 A GB0121585 A GB 0121585A GB 0121585 D0 GB0121585 D0 GB 0121585D0
Authority
GB
United Kingdom
Prior art keywords
asic
test pins
multiplexing test
multiplexing
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0121585A
Other versions
GB2379524A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Technologies UK Ltd
Original Assignee
NEC Technologies UK Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Technologies UK Ltd filed Critical NEC Technologies UK Ltd
Priority to GB0121585A priority Critical patent/GB2379524A/en
Publication of GB0121585D0 publication Critical patent/GB0121585D0/en
Publication of GB2379524A publication Critical patent/GB2379524A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
GB0121585A 2001-09-06 2001-09-06 Multiplexing pins on an ASIC Withdrawn GB2379524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0121585A GB2379524A (en) 2001-09-06 2001-09-06 Multiplexing pins on an ASIC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0121585A GB2379524A (en) 2001-09-06 2001-09-06 Multiplexing pins on an ASIC

Publications (2)

Publication Number Publication Date
GB0121585D0 true GB0121585D0 (en) 2001-10-24
GB2379524A GB2379524A (en) 2003-03-12

Family

ID=9921630

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0121585A Withdrawn GB2379524A (en) 2001-09-06 2001-09-06 Multiplexing pins on an ASIC

Country Status (1)

Country Link
GB (1) GB2379524A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602005006524D1 (en) 2004-01-13 2008-06-19 Nxp Bv JTAG TEST ARCHITECTURE FOR A MULTIPLE PACK
DE602005011967D1 (en) * 2005-09-09 2009-02-05 Infineon Technologies Ag JTAG port
GB0526448D0 (en) * 2005-12-23 2006-02-08 Advanced Risc Mach Ltd Diagnostic mode switching
CN109917277B (en) * 2019-05-16 2019-08-23 上海燧原智能科技有限公司 Virtual measuring method, device, equipment and storage medium

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5412260A (en) * 1991-05-03 1995-05-02 Lattice Semiconductor Corporation Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device
TW297096B (en) * 1995-06-07 1997-02-01 Ast Res Inc
JPH0991957A (en) * 1995-07-14 1997-04-04 Mitsubishi Electric Corp Mode selection circuit for semiconductor device
US5805608A (en) * 1996-10-18 1998-09-08 Samsung Electronics Co., Ltd. Clock generation for testing of integrated circuits
US6421812B1 (en) * 1997-06-10 2002-07-16 Altera Corporation Programming mode selection with JTAG circuits
US6430719B1 (en) * 1998-06-12 2002-08-06 Stmicroelectronics, Inc. General port capable of implementing the JTAG protocol

Also Published As

Publication number Publication date
GB2379524A (en) 2003-03-12

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)