GB0101590D0 - Clock synchronisation with timing adjust mode - Google Patents

Clock synchronisation with timing adjust mode

Info

Publication number
GB0101590D0
GB0101590D0 GBGB0101590.8A GB0101590A GB0101590D0 GB 0101590 D0 GB0101590 D0 GB 0101590D0 GB 0101590 A GB0101590 A GB 0101590A GB 0101590 D0 GB0101590 D0 GB 0101590D0
Authority
GB
United Kingdom
Prior art keywords
adjust mode
clock synchronisation
timing adjust
timing
synchronisation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0101590.8A
Other versions
GB2356090A (en
GB2356090B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP17071497A external-priority patent/JP4090088B2/en
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of GB0101590D0 publication Critical patent/GB0101590D0/en
Publication of GB2356090A publication Critical patent/GB2356090A/en
Application granted granted Critical
Publication of GB2356090B publication Critical patent/GB2356090B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
GB0101590A 1996-09-17 1997-09-10 Clock synchronisation with timing adjust mode Expired - Lifetime GB2356090B (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP24511896 1996-09-17
JP27009096 1996-10-11
JP33420896 1996-12-13
JP17071497A JP4090088B2 (en) 1996-09-17 1997-06-26 Semiconductor device system and semiconductor device
GB9719274A GB2317282B (en) 1996-09-17 1997-09-10 Input timing for semiconductor devices

Publications (3)

Publication Number Publication Date
GB0101590D0 true GB0101590D0 (en) 2001-03-07
GB2356090A GB2356090A (en) 2001-05-09
GB2356090B GB2356090B (en) 2001-06-20

Family

ID=27517425

Family Applications (4)

Application Number Title Priority Date Filing Date
GB0101590A Expired - Lifetime GB2356090B (en) 1996-09-17 1997-09-10 Clock synchronisation with timing adjust mode
GB0101588A Expired - Lifetime GB2356089B (en) 1996-09-17 1997-09-10 Clock synchronisation with timing adjust mode
GB0106448A Expired - Lifetime GB2357203B (en) 1996-09-17 1997-09-10 Clock synchronisation by inter-signal timing adjustment
GB0101592A Expired - Lifetime GB2356091B (en) 1996-09-17 1997-09-10 Clock adjustment using a dummy input circuit

Family Applications After (3)

Application Number Title Priority Date Filing Date
GB0101588A Expired - Lifetime GB2356089B (en) 1996-09-17 1997-09-10 Clock synchronisation with timing adjust mode
GB0106448A Expired - Lifetime GB2357203B (en) 1996-09-17 1997-09-10 Clock synchronisation by inter-signal timing adjustment
GB0101592A Expired - Lifetime GB2356091B (en) 1996-09-17 1997-09-10 Clock adjustment using a dummy input circuit

Country Status (1)

Country Link
GB (4) GB2356090B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4100300B2 (en) * 2003-09-02 2008-06-11 セイコーエプソン株式会社 Signal output adjustment circuit and display driver
CN104012002B (en) * 2011-12-29 2017-04-12 瑞萨电子株式会社 Semiconductor device
CN108573077B (en) * 2017-03-09 2022-01-25 深圳市中兴微电子技术有限公司 Method and device for adjusting signal deviation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2127594B (en) * 1982-09-18 1985-11-13 Int Computers Ltd Distribution of clock pulses
US4839907A (en) * 1988-02-26 1989-06-13 American Telephone And Telegraph Company, At&T Bell Laboratories Clock skew correction arrangement
KR910009808B1 (en) * 1989-06-13 1991-11-30 한국전기통신공사 Digital automatic phase control retiming circuit
US5467464A (en) * 1993-03-09 1995-11-14 Apple Computer, Inc. Adaptive clock skew and duty cycle compensation for a serial data bus
US5533072A (en) * 1993-11-12 1996-07-02 International Business Machines Corporation Digital phase alignment and integrated multichannel transceiver employing same
US5532632A (en) * 1994-02-01 1996-07-02 Hughes Aircraft Company Method and circuit for synchronizing an input data stream with a sample clock
US5486783A (en) * 1994-10-31 1996-01-23 At&T Corp. Method and apparatus for providing clock de-skewing on an integrated circuit board
TW340262B (en) * 1996-08-13 1998-09-11 Fujitsu Ltd Semiconductor device, system consisting of semiconductor devices and digital delay circuit

Also Published As

Publication number Publication date
GB2356090A (en) 2001-05-09
GB0101592D0 (en) 2001-03-07
GB0106448D0 (en) 2001-05-02
GB2356091A (en) 2001-05-09
GB0101588D0 (en) 2001-03-07
GB2356089B (en) 2001-06-20
GB2357203A (en) 2001-06-13
GB2356090B (en) 2001-06-20
GB2356089A (en) 2001-05-09
GB2357203B (en) 2001-07-25
GB2356091B (en) 2001-06-20

Similar Documents

Publication Publication Date Title
EP1147498A4 (en) Timing
GB2348555B (en) Clock synchronization
IL135642A0 (en) Timing circuit
GB9424018D0 (en) Clock synchronisation
GB9601348D0 (en) Clock synchronisation
GB2356090B (en) Clock synchronisation with timing adjust mode
GB2327161B (en) Timing circuit
GB2294561B (en) Circuit synchronization with multiple clock signals
GB2311628B (en) Clock
GB2319733B (en) Clock base
GB2307994B (en) Clock
GB9322609D0 (en) Clock synchronisation
GB9519814D0 (en) Clock
AU8989298A (en) Time clock with standpost structure
GB2325311B (en) Clock mechanism
GB2308206B (en) Clock
GB9604284D0 (en) Clocks
GB9400358D0 (en) Timing meants
TW303043U (en) Nine-star clock
GB9600074D0 (en) Clock
GB2318465B (en) Digital event timing
TW311702U (en) Clock watch structure
TW297512U (en) Foot-stand adjusting structure of photo-frame type clock
CA84912S (en) Clock
TW296071U (en) Improved timing mechanism of timer

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20150501 AND 20150506

PE20 Patent expired after termination of 20 years

Expiry date: 20170909