FR95737E - Static digital coding device. - Google Patents

Abstract

1,248,742. Position encoders. PRECILEC. 24 Oct., 1968 [24 Oct., 1967; 6 Sept., 1968], No. 50481/68. Heading G4H. A transducer measuring the relative position of two members to give an amplitude-significant signal and an analogue-digital converter digitizing the amplitude signal are fed with the same source as the reference signal. In the embodiment of Fig. 1 signals u 1 = E sin # . sin wt, u 2 = F cos # . sin wt, u 3 = - E sin # . sin wt and u 4 = - E cos # . sin wt representing the angular displacement # of the primary winding of resolver 10 are first compared with zero to determine which two signals are positive. The associated two comparators are then enabled to compare their two inputs with a stepped reference signal derived from voltage divider 6, each step being counted in an auxiliary counter 7 until one of the two comparators is operated. The logic circuit 5 then sets a counter 9 to a level dependent on which two comparators were initially enabled and which comparator operated first and counter 7 is counted down to 0, counter 9 being simultaneously incremented or decremented from its set level under the control of the logic circuit. The count is stored in a register 14 and may be displayed. The voltage divider (Fig. 3, not shown) comprises a parallel resistor chain the resistances being switched under the control of transistor switches operated by the outputs of counter 7. In the embodiment of Fig. 7 the signal from a potentiometer 18 representing the angular or linear position of its slider 17 are compared with four stepped reference voltages representing four possible ranges of the input. Initially the reference voltages have the values 0, v/4, v/2, 3v/4 to determine the range in which the input lies. The reference voltages are then stepped and as in the embodiment of Fig. 1 pulses simultaneously counted in auxiliary counter 7. The counter 9 is preset by the logic circuitry 5 in dependance on the range in which the input is found to be. The apparatus of Fig. 1 may be modified to include coarse and fine transducers, the coarse transducer giving twice the required resolution, i.e. an auxiliary digit 0 or 1 and the fine transducer dividing one coarse digit into a hundred increments. A logic circuit adds one to the coarse value if the auxiliary digit is " 1 " and the fine value is between 0 and 25 and subtracts 1 if the auxiliary coarse value is " 0 " and the fine value is between 75 and 99. Alternatively a three-stage system, i.e. coarse, fine and medium may be used.