FR81409E - Circuits logiques utilisant des inhibiteurs - Google Patents
Circuits logiques utilisant des inhibiteursInfo
- Publication number
- FR81409E FR81409E FR869187A FR869187A FR81409E FR 81409 E FR81409 E FR 81409E FR 869187 A FR869187 A FR 869187A FR 869187 A FR869187 A FR 869187A FR 81409 E FR81409 E FR 81409E
- Authority
- FR
- France
- Prior art keywords
- inhibitors
- logic circuits
- logic
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/381—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using cryogenic components, e.g. Josephson gates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/44—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using super-conductive elements, e.g. cryotron
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR869187A FR81409E (fr) | 1960-03-30 | 1961-07-27 | Circuits logiques utilisant des inhibiteurs |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18692A US3175197A (en) | 1960-03-30 | 1960-03-30 | Inhibitor logic arrays |
US46271A US3230354A (en) | 1960-03-30 | 1960-07-29 | Multi-level adder arrangement |
FR869187A FR81409E (fr) | 1960-03-30 | 1961-07-27 | Circuits logiques utilisant des inhibiteurs |
Publications (1)
Publication Number | Publication Date |
---|---|
FR81409E true FR81409E (fr) | 1963-09-20 |
Family
ID=27246113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR869187A Expired FR81409E (fr) | 1960-03-30 | 1961-07-27 | Circuits logiques utilisant des inhibiteurs |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR81409E (fr) |
-
1961
- 1961-07-27 FR FR869187A patent/FR81409E/fr not_active Expired
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