FR3117626B1 - Procédé d’allocation de mémoire pendant l’exécution d’un réseau de neurones - Google Patents
Procédé d’allocation de mémoire pendant l’exécution d’un réseau de neurones Download PDFInfo
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- FR3117626B1 FR3117626B1 FR2013373A FR2013373A FR3117626B1 FR 3117626 B1 FR3117626 B1 FR 3117626B1 FR 2013373 A FR2013373 A FR 2013373A FR 2013373 A FR2013373 A FR 2013373A FR 3117626 B1 FR3117626 B1 FR 3117626B1
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- 238000013528 artificial neural network Methods 0.000 title abstract 3
- 238000000034 method Methods 0.000 title abstract 3
- 239000000872 buffer Substances 0.000 abstract 3
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1041—Resource optimization
- G06F2212/1044—Space efficiency improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Biophysics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Artificial Intelligence (AREA)
- Data Mining & Analysis (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Computational Linguistics (AREA)
- Evolutionary Computation (AREA)
- Mathematical Physics (AREA)
- Software Systems (AREA)
- Neurology (AREA)
- Human Computer Interaction (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
- Devices For Executing Special Programs (AREA)
Abstract
Selon un aspect, un procédé est proposé pour définir des placements, dans une mémoire volatile, de mémoires tampons de travail temporaires utilisées pendant une exécution d’un réseau de neurones artificiels, le procédé comprenant les étapes suivantes : - déterminer (20) un ordre d’exécution des couches du réseau de neurones, - définir (21) des placements, dans une zone de mémoire de tas de la mémoire volatile, de mémoires tampons de résultats intermédiaires générées par chaque couche, selon l’ordre d’exécution des couches, - déterminer (22) au moins une région libre de la zone de mémoire de tas pendant l’exécution des couches, - définir (27) des placements de mémoires tampons de travail temporaires dans ladite au moins une région libre de la zone de mémoire de tas selon l’ordre d’exécution des couches. Figure pour l’abrégé : Fig 2
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2013373A FR3117626B1 (fr) | 2020-12-16 | 2020-12-16 | Procédé d’allocation de mémoire pendant l’exécution d’un réseau de neurones |
US17/455,770 US20220188610A1 (en) | 2020-12-16 | 2021-11-19 | Method for memory allocation during execution of a neural network |
EP21211915.0A EP4016311B1 (fr) | 2020-12-16 | 2021-12-02 | Procédé d'attribution de mémoire pendant l'exécution d'un réseau neuronal |
CN202111534114.0A CN114638350A (zh) | 2020-12-16 | 2021-12-15 | 用于神经网络执行期间的存储器分配的方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR2013373 | 2020-12-16 | ||
FR2013373A FR3117626B1 (fr) | 2020-12-16 | 2020-12-16 | Procédé d’allocation de mémoire pendant l’exécution d’un réseau de neurones |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3117626A1 FR3117626A1 (fr) | 2022-06-17 |
FR3117626B1 true FR3117626B1 (fr) | 2023-12-01 |
Family
ID=75438898
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR2013373A Active FR3117626B1 (fr) | 2020-12-16 | 2020-12-16 | Procédé d’allocation de mémoire pendant l’exécution d’un réseau de neurones |
Country Status (4)
Country | Link |
---|---|
US (1) | US20220188610A1 (fr) |
EP (1) | EP4016311B1 (fr) |
CN (1) | CN114638350A (fr) |
FR (1) | FR3117626B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20240020897A1 (en) * | 2022-07-12 | 2024-01-18 | Nvidia Corporation | Neural network-based image lighting |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1768002A1 (de) | 1968-03-20 | 1972-03-16 | Hoechst Ag | Harnstoffderivate,ihre Herstellung sowie Anwendung als Herbicide |
US10699186B2 (en) * | 2015-12-02 | 2020-06-30 | Google Llc | Determining orders of execution of a neural network |
KR102561261B1 (ko) * | 2017-11-14 | 2023-07-28 | 삼성전자주식회사 | 커널을 이용한 컨볼루션 연산 처리 방법 및 장치 |
FR3089649A1 (fr) | 2018-12-06 | 2020-06-12 | Stmicroelectronics (Rousset) Sas | Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones |
FR3094104A1 (fr) * | 2019-03-20 | 2020-09-25 | Stmicroelectronics (Rousset) Sas | Procédé et dispositif de détermination de la taille mémoire globale d’une zone mémoire globale allouée aux données d’un réseau de neurones compte tenu de sa topologie |
CN110162338B (zh) * | 2019-05-31 | 2020-08-04 | 中科寒武纪科技股份有限公司 | 运算方法、装置及相关产品 |
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2020
- 2020-12-16 FR FR2013373A patent/FR3117626B1/fr active Active
-
2021
- 2021-11-19 US US17/455,770 patent/US20220188610A1/en active Pending
- 2021-12-02 EP EP21211915.0A patent/EP4016311B1/fr active Active
- 2021-12-15 CN CN202111534114.0A patent/CN114638350A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
FR3117626A1 (fr) | 2022-06-17 |
CN114638350A (zh) | 2022-06-17 |
EP4016311B1 (fr) | 2024-05-01 |
US20220188610A1 (en) | 2022-06-16 |
EP4016311A1 (fr) | 2022-06-22 |
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