FR3117226B1 - Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant - Google Patents

Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant Download PDF

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Publication number
FR3117226B1
FR3117226B1 FR2012630A FR2012630A FR3117226B1 FR 3117226 B1 FR3117226 B1 FR 3117226B1 FR 2012630 A FR2012630 A FR 2012630A FR 2012630 A FR2012630 A FR 2012630A FR 3117226 B1 FR3117226 B1 FR 3117226B1
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FR
France
Prior art keywords
chip
mode
zone
microcontroller
managing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR2012630A
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English (en)
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FR3117226A1 (fr
Inventor
Sandrine Lendre
Hervé Cassagnes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR2012630A priority Critical patent/FR3117226B1/fr
Priority to US17/539,797 priority patent/US20220179810A1/en
Priority to CN202111458237.0A priority patent/CN114594850A/zh
Publication of FR3117226A1 publication Critical patent/FR3117226A1/fr
Application granted granted Critical
Publication of FR3117226B1 publication Critical patent/FR3117226B1/fr
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Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)

Abstract

Il est proposé en particulier de prévoir pour le système sur puce, un troisième mode de fonctionnement (MDF3) différent d’un mode de fonctionnement actif (MDF1) et d’un mode de fonctionnement (MDF2) basse consommation pour la globalité du système sur puce, ce troisième mode de fonctionnement étant un mode actif local pour au moins une zone particulière du système sur puce permettant aux autres zones du système sur puce de rester dans leur mode basse consommation. La zone particulière qui va être localement « réveillée » comporte un circuit d’accès direct en mémoire qui va pouvoir en particulier reconfigurer un ou plusieurs périphériques de cette zone réveillée. Figure pour l’abrégé : Fig 4
FR2012630A 2020-12-03 2020-12-03 Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant Active FR3117226B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR2012630A FR3117226B1 (fr) 2020-12-03 2020-12-03 Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant
US17/539,797 US20220179810A1 (en) 2020-12-03 2021-12-01 Method for managing the operation of a system on chip, for example a microcontroller, and corresponding system on chip
CN202111458237.0A CN114594850A (zh) 2020-12-03 2021-12-02 用于管理片上系统的操作的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2012630 2020-12-03
FR2012630A FR3117226B1 (fr) 2020-12-03 2020-12-03 Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant

Publications (2)

Publication Number Publication Date
FR3117226A1 FR3117226A1 (fr) 2022-06-10
FR3117226B1 true FR3117226B1 (fr) 2022-10-21

Family

ID=75339832

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2012630A Active FR3117226B1 (fr) 2020-12-03 2020-12-03 Procédé de gestion du fonctionnement d’un système sur puce, par exemple un microcontrôleur, et système sur puce correspondant

Country Status (2)

Country Link
US (1) US20220179810A1 (fr)
FR (1) FR3117226B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050276413A1 (en) * 2004-06-14 2005-12-15 Raja Neogi Method and apparatus to manage heterogeneous cryptographic operations
US8117475B2 (en) * 2006-12-15 2012-02-14 Microchip Technology Incorporated Direct memory access controller
US8487655B1 (en) * 2009-05-05 2013-07-16 Cypress Semiconductor Corporation Combined analog architecture and functionality in a mixed-signal array
US20150362980A1 (en) * 2014-06-16 2015-12-17 Apple Inc. Always-On Processor as a Coprocessor

Also Published As

Publication number Publication date
FR3117226A1 (fr) 2022-06-10
US20220179810A1 (en) 2022-06-09

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