FR3095073B1 - Codage de données sur bus série - Google Patents
Codage de données sur bus série Download PDFInfo
- Publication number
- FR3095073B1 FR3095073B1 FR1903929A FR1903929A FR3095073B1 FR 3095073 B1 FR3095073 B1 FR 3095073B1 FR 1903929 A FR1903929 A FR 1903929A FR 1903929 A FR1903929 A FR 1903929A FR 3095073 B1 FR3095073 B1 FR 3095073B1
- Authority
- FR
- France
- Prior art keywords
- serial bus
- data coding
- data
- coding
- transmitted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Quality & Reliability (AREA)
- Information Transfer Systems (AREA)
- Communication Control (AREA)
Abstract
Codage de données sur bus série La présente description concerne un procédé de codage d’une donnée (B) à transmettre sur un bus série SPI, dans lequel un registre (2) d’état d’une mémoire est modifié, à au moins un instant choisi, en fonction de tout ou partie de ladite donnée (B) à transmettre. Figure pour l'abrégé : Fig. 4
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1903929A FR3095073B1 (fr) | 2019-04-12 | 2019-04-12 | Codage de données sur bus série |
US16/840,759 US11321270B2 (en) | 2019-04-12 | 2020-04-06 | Data encoding on a serial bus |
CN202010281520.XA CN111813730A (zh) | 2019-04-12 | 2020-04-10 | 串行总线上的数据编码 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1903929 | 2019-04-12 | ||
FR1903929A FR3095073B1 (fr) | 2019-04-12 | 2019-04-12 | Codage de données sur bus série |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3095073A1 FR3095073A1 (fr) | 2020-10-16 |
FR3095073B1 true FR3095073B1 (fr) | 2021-03-12 |
Family
ID=67660280
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1903929A Active FR3095073B1 (fr) | 2019-04-12 | 2019-04-12 | Codage de données sur bus série |
Country Status (3)
Country | Link |
---|---|
US (1) | US11321270B2 (fr) |
CN (1) | CN111813730A (fr) |
FR (1) | FR3095073B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112527401A (zh) * | 2021-02-08 | 2021-03-19 | 北京紫光青藤微系统有限公司 | 存储器的启动方法、装置、电子设备及存储介质 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5630152A (en) * | 1992-05-18 | 1997-05-13 | Motorola, Inc. | Communication protocol between master and slave device with register information sharing |
EP1220229B1 (fr) * | 2000-12-29 | 2009-03-18 | STMicroelectronics S.r.l. | Une mémoire non volatile modifiable électriquement pouvant mémoriser une date jusqu'à-ce que la reprogrammation soit finie |
US20060248267A1 (en) * | 2005-04-29 | 2006-11-02 | Programmable Microelectronics Corporation | Flash memory having configurable sector size and flexible protection scheme |
CN103885908B (zh) * | 2014-03-04 | 2017-01-25 | 中国科学院计算技术研究所 | 一种基于外部设备可访问寄存器的数据传输系统及其方法 |
WO2015176040A1 (fr) * | 2014-05-15 | 2015-11-19 | Adesto Technologies Corporation | Dispositifs et procédé de mémoire ayant un accusé de réception d'instructions |
FR3041806B1 (fr) * | 2015-09-25 | 2017-10-20 | Stmicroelectronics Rousset | Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits |
CN105468563B (zh) * | 2015-12-28 | 2018-06-01 | 杭州士兰控股有限公司 | Spi从设备、spi通信系统及spi通信方法 |
TWI658465B (zh) * | 2018-02-02 | 2019-05-01 | 華邦電子股份有限公司 | 記憶體裝置以及其寫入/抹除方法 |
-
2019
- 2019-04-12 FR FR1903929A patent/FR3095073B1/fr active Active
-
2020
- 2020-04-06 US US16/840,759 patent/US11321270B2/en active Active
- 2020-04-10 CN CN202010281520.XA patent/CN111813730A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
FR3095073A1 (fr) | 2020-10-16 |
US11321270B2 (en) | 2022-05-03 |
US20200327092A1 (en) | 2020-10-15 |
CN111813730A (zh) | 2020-10-23 |
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