FR3091362B1 - Mémoire cache d’instructions dans un processeur à fils d’exécution multiples - Google Patents
Mémoire cache d’instructions dans un processeur à fils d’exécution multiples Download PDFInfo
- Publication number
- FR3091362B1 FR3091362B1 FR1906121A FR1906121A FR3091362B1 FR 3091362 B1 FR3091362 B1 FR 3091362B1 FR 1906121 A FR1906121 A FR 1906121A FR 1906121 A FR1906121 A FR 1906121A FR 3091362 B1 FR3091362 B1 FR 3091362B1
- Authority
- FR
- France
- Prior art keywords
- repeat
- cache
- instruction
- executed
- code
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
- G06F9/381—Loop buffering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/526—Mutual exclusion algorithms
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1028—Power efficiency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/45—Caching of specific data in cache memory
- G06F2212/452—Instruction code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
MÉMOIRE CACHE D’INSTRUCTIONS DANS UN PROCESSEUR À FILS D’EXÉCUTION MULTIPLES Processeur comprenant : une unité d’exécution à fils d’exécution en barillet pour exécuter des fils d’exécution simultanés, et une mémoire cache de répétition partagée entre les fils simultanés. Le jeu d’instructions du processeur comprend une instruction de répétition qui prend un opérande de compte de répétition. Lorsque la mémoire cache de répétition n’est pas réclamée et l’instruction de répétition est exécutée dans un premier fil, une portion de code est mise en mémoire cache à partir du premier fil dans la mémoire cache de répétition, l’état de la mémoire cache de répétition est changé pour l’enregistrer comme réclamée, et le code mis en mémoire cache est exécuté un certain nombre de fois. Lorsque l’instruction de répétition est ensuite exécutée dans un autre fil, la portion de code déjà mise en mémoire cache est de nouveau exécutée un nombre de fois respectif, à chaque fois à partir de la mémoire cache de répétition. Pour chacune de la première et des autres instructions, l’opérande de compte de répétition se trouvant dans l’instruction respective spécifie le nombre de fois qu’il faut exécuter le code mis en mémoire cache. Figure pour l'abrégé : Fig. 7
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1821229.0A GB2580316B (en) | 2018-12-27 | 2018-12-27 | Instruction cache in a multi-threaded processor |
GB1821229.0 | 2018-12-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3091362A1 FR3091362A1 (fr) | 2020-07-03 |
FR3091362B1 true FR3091362B1 (fr) | 2023-04-21 |
Family
ID=65364666
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1906121A Active FR3091362B1 (fr) | 2018-12-27 | 2019-06-07 | Mémoire cache d’instructions dans un processeur à fils d’exécution multiples |
Country Status (7)
Country | Link |
---|---|
US (2) | US11567768B2 (fr) |
JP (1) | JP6918051B2 (fr) |
CN (1) | CN111381883B (fr) |
CA (1) | CA3040901C (fr) |
DE (1) | DE102019112301A1 (fr) |
FR (1) | FR3091362B1 (fr) |
GB (1) | GB2580316B (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11314515B2 (en) * | 2019-12-23 | 2022-04-26 | Intel Corporation | Instructions and logic for vector multiply add with zero skipping |
CN112379928B (zh) * | 2020-11-11 | 2023-04-07 | 海光信息技术股份有限公司 | 指令调度方法以及包括指令调度单元的处理器 |
CN116090383A (zh) * | 2022-12-27 | 2023-05-09 | 广东高云半导体科技股份有限公司 | 实现静态时序分析的方法、装置、计算机存储介质及终端 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60241136A (ja) | 1984-05-16 | 1985-11-30 | Mitsubishi Electric Corp | デ−タ処理装置 |
JPH06243036A (ja) * | 1993-02-12 | 1994-09-02 | Hitachi Ltd | キャッシュ制御システム |
JPH07160585A (ja) | 1993-12-13 | 1995-06-23 | Hitachi Ltd | 低電力データ処理装置 |
JP2926045B2 (ja) | 1997-06-18 | 1999-07-28 | 松下電器産業株式会社 | マイクロプロセッサ |
US6567895B2 (en) * | 2000-05-31 | 2003-05-20 | Texas Instruments Incorporated | Loop cache memory and cache controller for pipelined microprocessors |
US7178013B1 (en) * | 2000-06-30 | 2007-02-13 | Cisco Technology, Inc. | Repeat function for processing of repetitive instruction streams |
US7065636B2 (en) | 2000-12-20 | 2006-06-20 | Intel Corporation | Hardware loops and pipeline system using advanced generation of loop parameters |
JP3796124B2 (ja) | 2001-03-07 | 2006-07-12 | 株式会社ルネサステクノロジ | スレッド間優先度可変プロセッサ |
GB0524720D0 (en) * | 2005-12-05 | 2006-01-11 | Imec Inter Uni Micro Electr | Ultra low power ASIP architecture II |
US7600076B2 (en) * | 2006-03-16 | 2009-10-06 | International Business Machines Corporation | Method, system, apparatus, and article of manufacture for performing cacheline polling utilizing store with reserve and load when reservation lost instructions |
US7987347B2 (en) | 2006-12-22 | 2011-07-26 | Broadcom Corporation | System and method for implementing a zero overhead loop |
JP5177141B2 (ja) | 2007-06-20 | 2013-04-03 | 富士通株式会社 | 演算処理装置、演算処理方法 |
US8868888B2 (en) * | 2007-09-06 | 2014-10-21 | Qualcomm Incorporated | System and method of executing instructions in a multi-stage data processing pipeline |
US20120079303A1 (en) | 2010-09-24 | 2012-03-29 | Madduri Venkateswara R | Method and apparatus for reducing power consumption in a processor by powering down an instruction fetch unit |
JP2011070695A (ja) | 2010-12-03 | 2011-04-07 | Hitachi Ltd | プロセッサ |
US8639882B2 (en) * | 2011-12-14 | 2014-01-28 | Nvidia Corporation | Methods and apparatus for source operand collector caching |
US9558000B2 (en) * | 2014-02-06 | 2017-01-31 | Optimum Semiconductor Technologies, Inc. | Multithreading using an ordered list of hardware contexts |
WO2016103092A1 (fr) * | 2014-12-22 | 2016-06-30 | Centipede Semi Ltd. | Parallélisation de code de temps d'exécution à contrôle continu de séquences d'instructions répétitives |
CN115100019A (zh) * | 2015-06-10 | 2022-09-23 | 无比视视觉技术有限公司 | 用于处理图像的图像处理器和方法 |
JP2017228213A (ja) * | 2016-06-24 | 2017-12-28 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US10241794B2 (en) | 2016-12-27 | 2019-03-26 | Intel Corporation | Apparatus and methods to support counted loop exits in a multi-strand loop processor |
CN114168526B (zh) | 2017-03-14 | 2024-01-12 | 珠海市芯动力科技有限公司 | 可重构并行处理 |
GB201717303D0 (en) | 2017-10-20 | 2017-12-06 | Graphcore Ltd | Scheduling tasks in a multi-threaded processor |
-
2018
- 2018-12-27 GB GB1821229.0A patent/GB2580316B/en active Active
-
2019
- 2019-02-15 US US16/276,895 patent/US11567768B2/en active Active
- 2019-04-23 CA CA3040901A patent/CA3040901C/fr active Active
- 2019-05-10 DE DE102019112301.1A patent/DE102019112301A1/de active Pending
- 2019-06-07 FR FR1906121A patent/FR3091362B1/fr active Active
- 2019-06-19 JP JP2019113318A patent/JP6918051B2/ja active Active
- 2019-06-25 CN CN201910559689.4A patent/CN111381883B/zh active Active
-
2022
- 2022-03-11 US US17/654,449 patent/US20220197645A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
GB2580316A (en) | 2020-07-22 |
CN111381883A (zh) | 2020-07-07 |
GB2580316B (en) | 2021-02-24 |
FR3091362A1 (fr) | 2020-07-03 |
CA3040901A1 (fr) | 2020-06-27 |
US20220197645A1 (en) | 2022-06-23 |
CA3040901C (fr) | 2021-05-04 |
JP2020107306A (ja) | 2020-07-09 |
CN111381883B (zh) | 2023-09-29 |
JP6918051B2 (ja) | 2021-08-11 |
DE102019112301A1 (de) | 2020-07-02 |
US20200210192A1 (en) | 2020-07-02 |
US11567768B2 (en) | 2023-01-31 |
GB201821229D0 (en) | 2019-02-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR3091362B1 (fr) | Mémoire cache d’instructions dans un processeur à fils d’exécution multiples | |
FR3072798B1 (fr) | Ordonnancement de taches dans un processeur a fils d'execution multiples | |
JP6469084B2 (ja) | コンピューティングシステムによって実行されるタスクの制御 | |
JP6526609B2 (ja) | プロセッサ | |
KR100498482B1 (ko) | 명령어수에 수행 주기 회수를 가중치로 사용하여 쓰레드를페치하는 동시 다중 쓰레딩 프로세서 및 그 방법 | |
Xu et al. | Influence of aging-induced flow waveform variation on hemodynamics in aneurysms present at the internal carotid artery: A computational model-based study | |
Lacassagne et al. | High level transforms for SIMD and low-level computer vision algorithms | |
WO2004068339A3 (fr) | Processeur a fil de pistage pour bandes laterales | |
RU2012148587A (ru) | Команда нетранзакционное сохранение | |
RU2008144192A (ru) | Многопоточная обработка электронных таблиц с использованием уровней зависимости | |
JP6450705B2 (ja) | 永続コミットプロセッサ、方法、システムおよび命令 | |
FR3091389B1 (fr) | Bancs de registres dans un processeur à fils d’exécution multiples | |
Lee et al. | Characterizing the latency hiding ability of gpus | |
Togashi et al. | Concurrency in Go and Java: performance analysis | |
JP2011528817A (ja) | パイプラインプロセッサ | |
JP2007287141A (ja) | プロセッサの動作を徐々に低速モードにするためのシステムおよび方法 | |
JP2018501535A (ja) | コンピューティング環境におけるスレッドの実行を制御する方法、システム、およびコンピュータ・プログラム | |
US20200285482A1 (en) | Post completion execution in an out-of-order processor design | |
Van Remoortel et al. | Evidence-Based Medicine: principles and values as illustrated by the case of Patient Blood Management | |
JP2004252670A (ja) | 共有リソースの競合検出器および共有リソースの競合検出方法 | |
JP6021112B2 (ja) | 複数のスレッドで順序付きトランザクションを実行する方法、並びに、当該トランザクションを実行するためのコンピュータ及びそのコンピュータ・プログラム | |
US10296315B2 (en) | Multiple-thread processing methods and apparatuses | |
US20070061633A1 (en) | Computer Processor Capable of Responding with Comparable Efficiency to Both Software-State-Independent and State-Dependent Events | |
JP2020099510A5 (fr) | ||
DE112010005459T5 (de) | Dynamisch rekonfigurierbarer prozessor und verfahren zum betreiben desselben |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 2 |
|
PLFP | Fee payment |
Year of fee payment: 3 |
|
PLFP | Fee payment |
Year of fee payment: 4 |
|
PLSC | Publication of the preliminary search report |
Effective date: 20220826 |
|
PLFP | Fee payment |
Year of fee payment: 5 |