FR3075430B1 - DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE - Google Patents

DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE Download PDF

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Publication number
FR3075430B1
FR3075430B1 FR1762655A FR1762655A FR3075430B1 FR 3075430 B1 FR3075430 B1 FR 3075430B1 FR 1762655 A FR1762655 A FR 1762655A FR 1762655 A FR1762655 A FR 1762655A FR 3075430 B1 FR3075430 B1 FR 3075430B1
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France
Prior art keywords
instructions
electronic device
data processing
processing method
executing
Prior art date
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Active
Application number
FR1762655A
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French (fr)
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FR3075430A1 (en
Inventor
Yannick Bequer
Philippe Andouard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia France SAS
Original Assignee
Oberthur Technologies SA
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Publication date
Application filed by Oberthur Technologies SA filed Critical Oberthur Technologies SA
Priority to FR1762655A priority Critical patent/FR3075430B1/en
Publication of FR3075430A1 publication Critical patent/FR3075430A1/en
Application granted granted Critical
Publication of FR3075430B1 publication Critical patent/FR3075430B1/en
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Storage Device Security (AREA)

Abstract

Un procédé de traitement de données mis en œuvre dans un dispositif électronique (1) équipé d'un processeur (2) comprend une étape d'exécution d'un premier ensemble d'instructions par le processeur (2) et une étape d'exécution d'un second ensemble d'instructions par le processeur (2). Entre l'étape d'exécution du premier ensemble d'instructions et l'étape d'exécution du second ensemble d'instructions, est exécutée une séquence d'instructions sélectionnée aléatoirement parmi une pluralité de séquences d'instructions ayant des durées d'exécution différentes. Au moins une des séquences d'instructions de ladite pluralité comprend des instructions conçues pour effectuer une opération de vérification du fonctionnement du dispositif électronique (1) lorsque ces instructions sont exécutées par le processeur (2).A data processing method implemented in an electronic device (1) equipped with a processor (2) comprises a step of executing a first set of instructions by the processor (2) and a step of executing a second set of instructions by the processor (2). Between the step of executing the first set of instructions and the step of executing the second set of instructions, a sequence of instructions selected randomly from among a plurality of sequences of instructions having execution times is executed. different. At least one of the instruction sequences of said plurality comprises instructions designed to perform an operation of verifying the operation of the electronic device (1) when these instructions are executed by the processor (2).

FR1762655A 2017-12-20 2017-12-20 DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE Active FR3075430B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1762655A FR3075430B1 (en) 2017-12-20 2017-12-20 DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1762655 2017-12-20
FR1762655A FR3075430B1 (en) 2017-12-20 2017-12-20 DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE

Publications (2)

Publication Number Publication Date
FR3075430A1 FR3075430A1 (en) 2019-06-21
FR3075430B1 true FR3075430B1 (en) 2020-08-07

Family

ID=62143278

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1762655A Active FR3075430B1 (en) 2017-12-20 2017-12-20 DATA PROCESSING METHOD AND ASSOCIATED ELECTRONIC DEVICE

Country Status (1)

Country Link
FR (1) FR3075430B1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2037857C (en) * 1990-03-20 2001-01-16 Roy Allen Griffin, Iii Prevention of determination of time of execution of predetermined data processing routine in relation to occurrence of prior observable external event
FR2874440B1 (en) * 2004-08-17 2008-04-25 Oberthur Card Syst Sa METHOD AND DEVICE FOR PROCESSING DATA

Also Published As

Publication number Publication date
FR3075430A1 (en) 2019-06-21

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