FR3075420A1 - SYSTEM AND METHOD FOR SECURE STARTING A PROCESSOR - Google Patents

Abstract

 This system (300) for securely starting a processor (310), the system comprising the processor and the processor using, when it is reset, a reset program (L1) present in a storage space, is characterized in that the storage space is a volatile storage space (320), and in that the system further includes a security processor (330) and a secure storage space (340), the security processor being configured to : applying to the processor a reset signal (Sr) whose level inhibits the reset of the processor; load a reset program (L1) from the secure storage space in the volatile storage space; and change the level of the reset signal (Sr) to allow the processor to reset.

Description

SYSTEM AND METHOD FOR SECURE STARTING OF A PROCESSOR

The present invention relates to resetting a processor.

More particularly, the invention relates to securing the reset program used when the processor starts.

As shown in FIG. 1, in a conventional manner, a processor 10 enters into a reset procedure when receiving a reset signal Sr produced by a control module 5, for example when powering up the card electronics comprising the processor 10. For the reset, the processor 10 accesses the non-volatile storage space 20 to load a reset program L1, called the “boot” program in English. The non-volatile storage space 20 includes an interface 22 connected to a conjugate interface 12 of the processor 10 via a bus 15. The processor once reset can then load other programs of the operating system or application type.

This reset procedure poses the risk that the reset program is corrupted. For example, and in an extreme case, a computer virus is integrated into the reset program which is memorized in the factory in the non-volatile storage space. It is then no longer possible to verify the integrity of the reset program used by the processor during a restart. If the reset program is found to be corrupt, the non-volatile storage space should be replaced. If the electronic card does not allow it, the whole system must be replaced.

The object of the present invention is therefore to solve this problem.

For this, the subject of the invention is a secure system for starting a processor, the system comprising the processor and the processor using, when it is reset, a reset program present in a storage space, characterized in that the storage space is a volatile storage space, and in that the system further comprises a security processor and a secure storage space, the security processor being configured to: apply to the processor a reset signal whose level inhibits processor reset; load a reset program from the secure storage space in the volatile storage space, and, once the reset program is loaded in the volatile storage space, modify the level of the reset signal to allow the processor to be reset .

According to particular embodiments, the system includes one or more of the following characteristics, taken in isolation or according to all technically possible combinations:

- the volatile storage space comprises: a first interface, connected to a first processor interface and dedicated to resetting the processor, and a second interface, connected to a second interface of the security processor and dedicated to loading the reset program .

- the volatile storage space comprises a single interface, which is connected to both a first interface of the processor and a second interface of the security processor, the security processor being clean, once the reset program has been loaded into the volatile storage space, increasing an impedance of the second interface of the security processor so that the processor can communicate with the single interface of the volatile storage space.

- The system further comprises a buffer unit placed in cutoff between the single interface of the volatile storage space and the first interface of the processor, the security processor being configured to apply a control signal to the buffer unit taking: a first level suitable for placing the buffer unit in a blocking state so that the single interface of the volatile storage space is decoupled from the first interface of the processor in order to allow the loading of the reset program in space volatile storage by the security processor; or a second level suitable for placing the buffer unit in a passing state so that the interface of the volatile storage space is coupled to the first interface of the processor to allow the processor to access the volatile storage space.

- the security processor is configured to check the integrity of the reset program.

The subject of the invention is also a method for secure starting of a processor implemented by a system conforming to the preceding system, comprising the steps consisting in: inhibiting a reset of the processor by means of the application, by a security processor , a reset signal placed in an active level; loading, by the security processor, a reset program from a secure storage space to a volatile storage space; authorize the reset of the processor by means of the application, by the security processor, of the reset signal placed in an inactive level; and reset the processor from the reset program present in the volatile storage space.

According to particular embodiments, the method comprises one or more of the following characteristics, taken in isolation or according to all technically possible combinations:

- The method includes an additional step during which the security processor verifies the integrity of the reset program.

the method further comprises the steps consisting in, when the volatile storage space comprises a multi-master interface for connection to a common bus: before loading the reset program in the volatile storage space, the processor security lowers an impedance of a second interface for connecting the security processor to the common bus; and, after loading the reset program into the volatile storage space, the security processor increases the impedance of the second interface for connecting the security processor to the common bus.

the method comprises, when the system comprises a buffer unit placed in the cut-off between a single interface of the volatile storage space and the first interface of the processor, the steps: before loading the reset program in the volatile storage space , application, by the security processor, of a control signal having a first level to place the buffer unit in a blocking state so that the single interface of the volatile storage space is decoupled from the first interface of the processor and allows the loading of the reset program into the volatile storage space by the security processor; after loading the reset program into the volatile storage space, application, by the security processor, of the control signal having a second level to place the buffer unit in a on state so that the single interface for the volatile storage space is coupled to the first interface of the processor and allows the processor to access the volatile storage space for resetting.

The invention and its advantages will be better understood on reading the detailed description which follows of a particular embodiment, given solely by way of nonlimiting example, this description being made with reference to the appended drawings in which:

- Figure 1 is a schematic representation of a system according to the state of the art comprising a processor associated with a non-volatile storage space memorizing the reset program that the processor uses on each reset;

- Figure 2 is a first embodiment of the system according to the invention;

- Figure 3 is a second embodiment of the system according to the invention;

- Figure 4 is a third embodiment of the system according to the invention;

FIG. 5 is a representation in the form of blocks of the method implemented by the systems of FIGS. 2 to 4.

In general, the invention consists in associating a volatile storage space with the processor to be secured, and in providing the system with a security processor and with a secure storage space.

The security processor inhibits the reinitialization of the processor while copying, from the secure storage space to the volatile storage space, the reinitialization program which the processor to use must secure.

Advantageously, the security processor verifies the integrity of the reset program which it copies into the volatile storage space.

As soon as the reset program is loaded, the security processor authorizes the reset of the processor.

When resetting, the processor then uses the reset program that has just been loaded into the volatile storage space.

A volatile storage space is a space which, each time the power is turned off, loses the data it stores or, more generally, whose data it stores are replaced by random data, which cannot be used. A volatile storage space presents a reduced blow.

The security processor is a trusted processor. How to guarantee the safety of the security processor and of the non-volatile storage space associated with it is outside the scope of the present invention.

FIG. 2 represents a first embodiment of the system according to the invention.

The system 100 includes a processor 110 to be secured, a volatile storage space 120, a security processor 130 and a secure storage space 140.

The security processor 130 is connected directly to the processor 110 so as to apply a reset signal Sr to a suitable tab of the processor 110.

The reset signal Sr is a binary signal, which is either in an active state, inhibiting the reset of the processor 110, or in the inactive state authorizing the reset of the processor 110.

By default, the reset signal Sr is in the active level in order to avoid an unwanted reset of the processor when the electronic card is powered up. Indeed, if on the contrary the reset signal Sr was by default in the inactive level, the following risk would exist: in the case where the power supply of the processor 110 is present before that of the security processor 130, the reset signal, in the inactive level, would allow a reset of the processor 110 before the security processor has started and it can modify the level of the reset signal to inhibit the reset of the processor.

In this first embodiment, the volatile storage space 120 has several interfaces.

It thus comprises a first interface 122, which is connected, by a dedicated bus 115, to a first conjugate interface 112 of the processor 110.

The volatile storage space 120 also includes a second interface 124, which is connected, by a dedicated bus 117, to a second conjugate interface 134 of the security processor 130.

The secure storage space 140 includes a third interface 142, which is connected, by a dedicated bus 135, to a third conjugated interface 132 of the security processor 130.

The secure storage space 140 stores a first reset program L1 for resetting the processor 110 and, advantageously, a second reset program L2 for resetting the security processor 130.

Referring to Figure 5, the method 500, implemented by the system 100, is as follows.

Following, for example, the powering up of the electronic card on which the system 100 is installed, in step 510, the security processor 130 inhibits the reset of the processor 110 by the application of a reset signal Sr being in the active level.

In step 512, the security processor 130 executes its own reinitialization process from the second reinitialization program L2 loaded from the secure storage space 140. The program L2 allows for example to provide the security processor 130 with a copy functionality and a verification functionality of the first reset program L1.

In step 516, the security processor 130 copies the first reset program L1 from the secure storage space 140 to the volatile storage space 120.

Advantageously, during the copying step 216, the security processor 130, in a step 517, executes the functionality for verifying the integrity of the first reset program L1. It can be an authentication, decryption, bit-by-bit comparison program or any other procedure known to a person skilled in the art to ensure that the first reset program L1 is not corrupt.

The copying step 516 ends when the entire first reset program L1 has been loaded into the volatile storage space 120. The end of this loading is for example determined by the security processor 130 when it has transferred a certain volume of data, for example indicated in the copy functionality.

As soon as the transfer of the first reset program L1 from one storage space to the other is completed, in step 520, the security processor 130 modifies the level of the reset signal Sr, to apply a reset signal Sr in the inactive level, so as to authorize the reinitialization of the processor 110.

In step 522 of resetting the processor 110, the latter accesses the volatile storage space 120 and loads the first reset program L1 which has been deposited there.

FIG. 3 represents a second embodiment of the system according to the invention.

The system 200 includes a processor 210 to be secured, a volatile storage space 220, a security processor 230 and a secure storage space 240.

The security processor 230 is connected directly to the processor 210 so as to apply, on a tab of the latter, a reset signal Sr.

The reset signal Sr is a binary signal having an active level, inhibiting the reset of the processor 210, and an inactive level, authorizing the reset of the processor 210. By default, the reset signal Sr applied to the processor 210 is in the level active.

The volatile storage space 220 comprises, in this second embodiment, a single interface 222, which is connected by a common bus 216 to both a first interface 212 of the processor 210 and a second interface 234 of the security processor 230. The interface 222 is therefore a multi-master interface.

The secure storage space 240 comprises a third interface 242 connected, by a dedicated bus 235, to a third conjugated interface 232 of the security processor 230.

The secure storage space 240 stores a first reset program L1 for resetting the processor 210 and, preferably, a second reset program L2 for resetting the security processor 230.

The method implemented by the system 200 is similar to that implemented by the system 100. It only includes the following additional steps.

In step 514 (cf. FIG. 5), before starting the copying step of the first reset program 210 in the volatile storage space 220, the security processor 230 lowers the impedance of its second interface 234 to , while the processor 210 is inhibited, check the common bus 216.

Symmetrically, in step 518, after the copying step 516, the security processor 230 increases the impedance of its second interface 234 so that the processor 210, once uninhibited, can control the common bus 216.

In this way, competition between the processors in communication with the volatile storage space 220 is avoided.

It is indeed necessary for the first interface 212 of the processor 210 to be at high impedance when the processor 210 is inhibited so as not to disturb the communication between the security processor 230 and the volatile storage space 220.

FIG. 4 represents a third embodiment of the system according to the invention.

The system 300 comprises a processor 310, a volatile storage space 320, a security processor 330, a secure storage space 340 and a buffer unit 350.

The security processor 330 is connected directly to the processor 310 so as to apply to it a reset signal Sr.

The reset signal Sr is a binary signal having an active level, inhibiting the reset of the processor 310, and an inactive level, authorizing the reset of the processor 310. By default, the security processor 330 delivers a reset signal Sr of active level , especially during its own reset and writing to volatile storage 320.

The volatile storage space 320 comprises a single interface 322 connected, by a common bus 319, to a fourth interface 354 of the buffer unit 350 and to a second interface 334 of the security processor 330.

The secure storage space 340 comprises a third interface 342 connected, by a dedicated bus 335, to a third conjugated interface 332 of the security processor 330.

The buffer unit 350 also comprises a fifth interface 352, which is connected, by a dedicated bus 318, to a first interface 312 of the processor 310.

The secure storage space 340 stores a first reset program L1 for resetting the processor 310 and, preferably, a second reset program L2 for resetting the security processor 330.

Finally, the security processor 330 is connected directly to the buffer unit 350 so as to apply, to an appropriate input of the buffer unit 350, a control signal Su.

The control signal Su is a binary signal having:

a first level, suitable for placing the buffer unit 350 in a blocking state so that the single interface 322 of the volatile storage space 320 is decoupled from the first interface 312 of the processor 310; and,

a second level, suitable for placing the buffer unit 350 in a passing state so that the single interface 322 of the volatile storage space 320 is coupled to the first interface 312 of the processor 310 to allow the latter to access to volatile storage space.

In the blocking state, the buffer unit 350 sets the impedance of the fourth interface 354 to a high value so as not to disturb the communication between the security processor 330 and the volatile storage space 320, in particular during of the copying step of the first reset program L1.

In the on state, the buffer unit 350 sets the impedance of the fourth interface 354 to a low value so that the buffer unit 350 can access, via the bus 319, the volatile storage space 320 , the security processor 330 then being capable of raising the impedance of the second interface 334 so as not to interfere with the communication between the buffer unit 350 and the volatile storage space 320.

The method implemented by the system 300 is similar to that implemented by the system 100. It only includes the following additional steps.

In step 514, before starting step 516 of copying the first reset program L1 into the volatile storage space 320, the security processor 330 first applies a control signal Su in the first level so that the buffer unit 350 is in the blocking state and places the impedance of the fourth interface 354 at a high value. Then the security processor 330 lowers the impedance of its second interface 334 in order, while the processor 310 is inhibited, to control the common bus 319.

Symmetrically, in step 518, after the copying step 516, the security processor 330 first increases the impedance of its second interface 334 and then applies a control signal Su in the second level so that the the buffer unit 350 is in the on state and sets the impedance of the fourth interface 354 to a low value, so that the buffer unit 350 controls the bus 319.

As soon as the security processor 330 to modify the level of the reset signal Sr so that it is in the inactive level, in step 522 the processor 310 starts by accessing the volatile storage space 320 via of the buffer unit 350. More precisely, any command applied to the fifth interface 352 is reissued by the fourth interface 354 and any command applied to the fourth interface 354 is reissued by the fifth interface 352. The processor 310 thus loads the first program reset L1, the buffer unit 350 then being essentially transparent.

This last embodiment has the following advantage. When an active level reset signal Sr is applied to the processor 310, the impedance state of the first interface 312 is in fact not defined. It can in particular be in a low impedance state disrupting communication on the common bus, in particular between the security processor 330 and the volatile storage space 220. By placing a buffer unit 350 at the cutoff of the processor interface 310 and the common bus 319 and by controlling the impedance of the interface of the buffer unit on this common bus, the quality of the communication between the security processor 330 and the volatile storage space 320 is guaranteed, and therefore the error-free copying of the first reset program L1.

Those skilled in the art will understand that the systems and methods just presented make it possible to secure the reset program used for starting a processor.

In the present document, a storage space can be any type of storage space known to a person skilled in the art. A volatile storage space can for example be a random access memory (RAM for “Random Access Memory”), a programmable logic component (in particular an FPGA for “Field-Programmable Gate Array”), etc. A non-volatile storage space can for example be a single access memory (ROM for “Read Only Memory”), a Flash memory, etc.

In the embodiment of Figure 2, the volatile storage space having two interfaces, it is rather a programmable logic component rather than a memory. Alternatively, other components can be used, for example Dual-Port memories of the SRAM type. However, the use of a programmable logic component allows more flexibility in the implementation.

In the present document, a processor can be any type of component known to a person skilled in the art. It can for example be a microprocessor, an application-specific integrated circuit (ASIC for "application-Specific Integrated Circuit"), a programmable component type FPGA, etc.

It should be noted that the present solution is based on the assumption that the speed of the security processor is insufficient to drive the bus so as to allow direct transfer of the reset program L1 from the non-volatile storage space associated with the processor. security to the main processor. It is therefore necessary to go through an intermediate volatile storage space.

In the present document, a bus can be any type of bus known to a person skilled in the art. It can for example be a SPI bus ("Serial Peripheral Interface"), a 10 I2C bus ("Inter-integrated Circuit"), etc.

Claims (9)

1. -System (100, 200, 300) for secure start-up of a processor (110, 210, 310), the system comprising the processor and the processor using, during its reset, a reset program (L1) present in a storage space, characterized in that the storage space is a volatile storage space (120, 220, 320), and in that the system further comprises a security processor (130, 230, 330) and a secure storage space (140, 240, 340), the security processor being configured to: - applying to the processor a reset signal (Sr) whose level inhibits the reset of the processor; - load a reset program (L1) from the secure storage space in the volatile storage space; and, once the reset program is loaded into volatile storage, - modify the level of the reset signal (Sr) to allow the processor to reset. 2. - System (100) according to claim 1, in which the volatile storage space (120) comprises: - a first interface (122), connected to a first interface (121) of the processor (110) and dedicated to resetting the processor; and - a second interface (124), connected to a second interface (234) of the security processor (130) and dedicated to loading the reset program (L1). 3. - System (200, 300) according to claim 1, in which the volatile storage space (220, 320) comprises a single interface (222, 322), which is connected both to a first interface (212, 312) of the processor (210, 310) and a second interface (234, 334) of the security processor (230, 330), the security processor being clean, once the reset program (L1) is loaded in the space of volatile storage, increasing an impedance of the second interface (234, 334) of the security processor so that the processor can communicate with the single interface (222, 322) of the volatile storage space. 4. - System (300) according to claim 3, further comprising a buffer unit (350) placed in cut between the single interface (322) of the volatile storage space (320) and the first interface (312 ) of the processor (310), the security processor (330) being configured to apply a control signal (Su) to the buffer unit (350) taking: - A first level suitable for placing the buffer unit (350) in a blocking state so that the single interface (322) of the volatile storage space (320) is decoupled from the first interface (312) of the processor (310 ) in order to allow the loading of the reset program (L1) into the volatile storage space by the security processor; or, - a second level suitable for placing the buffer unit (350) in a passing state so that the interface (322) of the volatile storage space (320) is coupled to the first interface (312) of the processor (310) to allow the processor to access volatile storage space. 5, - System (100, 200, 300) according to any one of claims 1 to 4, in which the security processor (130, 230, 330) is configured so as to verify the integrity of the reset program (L1 ). 6, - Method for secure starting of a processor (110) implemented by a system according to any one of claims 1 to 5, comprising the steps consisting in: - inhibiting (510) a reset of the processor (110) by means of the application, by a security processor (130), of a reset signal (Sr) placed in an active level; - loading (516), by the security processor (130), a reset program (L1) from a secure storage space (140) to a volatile storage space (120); - authorize (520) the reset of the processor (110) by means of the application, by the security processor (130), of the reset signal (Sr) placed in an inactive level; and, - reset (522) the processor (110) from the reset program (L1) present in the volatile storage space (120). 7, - Method according to claim 6, comprising an additional step (517) during which the security processor (130) verifies the integrity of the reset program (L1). 8. - Method according to claim 6 or claim 7, further comprising the steps consisting in, when the volatile storage space (220) comprises a multi-master interface for connection to a common bus (216): - before loading the reset program (L1) into the volatile storage space (220), the security processor (230) lowers an impedance of a second interface (234) for connecting the security processor (230) to the common bus; and, - after loading the reset program (L1) in the volatile storage space (220), the security processor (230) increases the impedance of the second interface (234) for connecting the security processor (230) to the common bus. 9. - Method according to claim 8, comprising, when the system comprises a buffer unit (350) placed in the cut between a single interface (322) of the volatile storage space (320) and the first interface (312) of the processor (310), the steps: - before loading the reset program (L1) into the volatile storage space (320), application, by the security processor (330), of a control signal (Su) having a first level for placing the buffer unit (350) in a blocking state so that the single interface (322) of the volatile storage space (320) is decoupled from the first interface (312) of the processor (310) and allows the loading of the program reset (L1) in the volatile storage space by the security processor; - after loading the reset program (L1) into the volatile storage space (320), application, by the security processor (330), of the control signal (Su) having a second level for placing the buffer unit (350) in a on state so that the single interface (322) of the volatile storage space (320) is coupled to the first interface (312) of the processor (310) and allows the processor to access volatile storage space for resetting.