FR3069375A1 - OPTIMIZED DOUBLE GRID TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - Google Patents

Abstract

The subject of the invention is an integrated circuit comprising: at least one nMOS transistor and at least one pMOS transistor; at least one mutually dopable or buried semiconductor background plane common to said nMOS transistor and to said pMOS transistor, said transistors comprising a layer of semiconductor material disposed over a buried insulator layer; at least one gate insulator and a gate common to said nMOS transistor and to said pMOS transistor; at least one shared contact electrically contacting said common gate and said common rear plane, said shared contact crossing the buried insulator layer or an insulation defined between said nMOS transistor and said pMOS transistor.

Description

Optimized double gate transistors and manufacturing process

The field of the invention is that of integrated circuits and more precisely that of MOS transistors (for "metal oxide semiconductor") using FDSOI technology (for "Fully Depleted Silicon On Insulator") designating silicon completely deserted on insulator) and comprising a polarized rear plane disposed between a very thin insulating oxide layer and a very thin active layer, commonly called UTBB (for Ultra Thin Body and BOX).

It is known that the simultaneous polarization of the gate of a transistor and its rear plane (commonly called ground plane) improves the performance of the transistors, at least in static regime. The term back plane generally designates an n-doped or p-doped region isolated in a semiconductor, it can also be defined by the term box. One thus designates “double gate” transistors.

It has been described in particular in the article: “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond”, F. Andrieu, O. Weber, J. Mazurier, O Thomas, JP. Noël, C. Fenouillet-Béranger, J-P. Mazellier, P. Perreau, T. Poiroux, Y. Morand *, T. Morel, S. Allegret *, V. Loup, S. Barnola, F. Martin, JF. Damlencourt, I. Servin, M. Cassé, X. Garros, O. Rozeau, M-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Délayé, C. Tabone, L. Tosti, L. Brévard, P. Gaud, V. Paruchuri #, K.K. Bourdelle +, W. Schwarzenbach +, O. Bonnin +, B-Y. Nguyen +, B. Doris #, F. Boeuf *, T. Skotnicki *, O. Faynot, CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, ST Microelectronics, 850 rue Monnet, F-38926 Crolles; # IBM Research, Albany, NY 12203; + SOITEC, Parc Technologiques des Fontaines F-38926 Bernin, 978-1-4244-76411 / 10 / $ 26.00 © 2010 IEEE 2010 Symposium on VLSI Technology Digest of Technical Papers, current performance as a function of voltage obtained with a simple transistor gate and with a double gate transistor. Figure 1 shows the performance obtained (the “dash: SG mode” curves relate to a single grid configuration, the “full: DG mode >> curves relate to a double grid configuration).

In particular, the SRAMs memories can be improved by this operating mode.

There have also been proposed configurations for addressing sets of pMOS and nMOS transistors, as in the article: “UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below” L. Grenouillet ¹ , M Vinet ¹ , J. Gimbert ² , B. Giraud ¹ , JP Noël ² , Q. Liu ² , P. Khare ² , MA Jaud ¹ , Y. Le Tiec ¹ , R. Wacquez ¹ , T. Levin ³ , P. Rivallin ¹ , S. Holmes ³ , S. Liu ³ , KJ Chen ³ , O. Rozeau ¹ , P. Scheiblin ¹ , E. McLellan ³ , M. Malley ³ , J. Guilford ³ , A. Upham3, R. Johnson ³ , M. Hargrove ⁴ , T. Hook ³ , S. Schmitz ³ , S. Mehta ³ , J. Kuss ³ , N. Loubet ² , S. Teehan ³ , M. Terrizzi3, S. Ponoth ³ , K. Cheng ³ , T. Nagumo ⁵ , A. Khakifirooz ³ , F. Monsieur ² , P. Kulkarni ³ , R. Conte ³ , J. Demarest ³ , O. Faynot ¹ , W. Kleemeier ² , S. Luning ⁴ , B. Doris ³ , ¹ CEA-LETI, ² STMicroelectronics, ³ IBM, 4 GLOBALFOUNDRIES, 5Renesas, 257 Fuller Rd, 12203 Albany, NY, USA, 978-1 -4673-4871 -3 / 12 / $ 31.00 © 2012 IEEE.

In general, it is necessary to provide for the operation of the different transistors, to electrically isolate them from each other. This is why, the transistors are generally surrounded by isolation trenches designated by the acronym STI for "Shallow Trench Isolation". In the article by L. Grenouillet et al., It is proposed as illustrated in FIG. 4 of this article and reported in FIG. 2 of the patent application, to carry out deep insulations "STI" for "Shallow Trench Isolation >> between the nMOS transistors and the pMOS transistors to isolate their box and shallow "STIs" between the MOS transistors of the same type to isolate the active regions (source / drain) of the transistors.

In the present application, an MOS transistor is designated as being an insulated gate field effect transistor more commonly called MOSFET (English acronym for Metal Oxide Semiconductor Field Effect Transistor - which translates as field effect transistor with metaloxide-semiconductor structure ), The nMOS transistor has an electron channel, the pMOS transistor has a hole channel.

In general, it should be possible to connect the lower rear plane and the upper gates as illustrated in FIGS. 3a to 3e which show a set of pMOS transistors and nMOS transistors as well as the grid contacts and rear plane contact.

More specifically, FIG. 3a highlights, the grid contacts and the lower rear plane contacts GP, the problem posed remaining being to connect the rear plane and the grid without adding a dedicated rear plane contact for each rear plane.

The top view illustrated in FIG. 3a also highlights an active region in which grids are continuous between the nMOS and pMOS zones, and shows a region called “hybrid” with taps on the substrate.

FIGS. 3b to 3e show, the rear plane used as the rear grid of the transistors to be polarized nevertheless requiring:

- adjacent transistors which have opposite type boxes;

- boxes of adjacent transistors in contact.

The isolation of the boxes is therefore made by a diode, which limits the range of polarization of the boxes.

In this context, the subject of the present invention is a configuration of nMOS and pMOS transistors comprising zones of shallow isolation between the nMOS transistors and the pMOS transistors so as to be able to use a shared contact between the gates (common to the nMOS and pMOS transistors ) and the common rear planes or rear lines between nMOS transistors and pMOS transistors.

It should be noted that in the configurations of the prior art, and in particular in the configurations described in the article by L. Grenouillet et al (previously cited), it is proposed, on the contrary, to use deep "STI" isolations. between the nMOS transistors and the pMOS transistors to isolate their box and a shallow “STI” isolation between the MOS of the same type to isolate the active regions (defined between the sources and the drains of the transistors).

One of the main advantages of the present invention thus lies in the development of shared contact between grid and rear plane at the level of the double-grid structure.

More specifically, the subject of the present invention is an integrated circuit comprising:

- a substrate;

- a layer of buried insulation;

- at least one nMOS transistor comprising a layer of semiconductor material disposed above said layer of buried insulator;

- at least one pMOS transistor comprising a layer of semiconductor material disposed above said layer of buried insulator;

- at least one semiconductor rear plane that can be doped or metallic disposed above the substrate and below the buried insulating layer, said buried plane being common to said nMOS transistor and to said pMOS transistor;

at least one gate insulator and one gate common to said nMOS transistor and to said pMOS transistor and situated above the channel of these transistors and opposite said rear plane, the surface of the rear plane covering at least the surface of the grid in vertical projection ;

said nMOS transistor being separated from said pMOS transistor by an insulation defined between said layer of semiconductor material of said nMOS transistor and said layer of semiconductor material of said pMOS transistor, said insulation being located in said layer of buried insulator and in contact with said rear plane;

- At least one shared contact electrically contacting said common grid and said common rear plane, said shared contact passing through the buried insulating layer or said insulation.

In general, in the present application, when the integrated circuit comprises several nMOS transistors and several pMOS transistors, the following two cases are considered:

- the rear plane can be common to several nMOS transistors and to several pMOS transistors, the grids present a projection at the same rear plane;

- when the rear plane is of limited extension, it is designated by the term rear line, facing a transistor gate, the gates present a projection facing the rear lines.

According to variants of the invention, said shared contact is located between said nMOS transistor and said pMOS transistor.

According to variants of the invention, the buried plane is defined in a doped semiconductor region called a box, of the type opposite to that of said rear plane, said rear plane being doped semiconductor.

According to variants of the invention, the circuit comprises several nMOS transistors, several pMOS transistors, common rear lines between an nMOS transistor and a pMOS transistor, said rear lines being opposite said common gates and being separated by a dielectric.

It is notably known that in a logic circuit the source of an nMOS transistor is connected to ground and that of a pMOS transistor is connected to the supply voltage. The fact of not making the rear line extend beyond the side of the drains of the transistors reduces the parasitic capacitances between the rear line and the drain and therefore improves the dynamic performance of the circuits. Overflows on the drain side are more disadvantageous than on the source side in dynamic performance.

It can therefore be very advantageous to provide a circuit configuration in which there is no overflow of the rear line on the drain side.

This is why, according to variants of the invention, the integrated circuit comprises rear lines which do not project in vertical projection relative to said gates of said nMOS and pMOS transistors on the side of the drains of said nMOS and pMOS transistors.

According to variants of the invention, the circuit comprises rear lines off-center on the source side of said transistors with respect to said gates of said nMOS and pMOS transistors so as not to be opposite the drains of said nMOS and pMOS transistors.

According to variants of the invention, the circuit comprises at least two adjacent nMOS transistors and at least two adjacent pMOS transistors, said adjacent nMOS transistors and said adjacent pMOS transistors having a common source between transistors of the same type and a common rear line which is superimposed in vertical projection on the gates of the two said nMOS and pMOS transistors and on the common source.

In such a configuration, it can also be advantageous for said rear line not to project in vertical projection with respect to said gates on the side of the drains of said nMOS and pMOS transistors.

According to the present invention, said rear plane is electrically isolated from said substrate and laterally from the environment.

The advantage of integrating rear lines (corresponding to the smallest possible dimension) is to maintain an overlap with respect to the upper grid, so as to benefit from better electrostatic control while reducing the extension of the rear plane under the Source / Drain of the transistor and the parasitic capacities between the rear plane and the source / drain (capacities which decrease the dynamic performances (= speed) of the logic gates).

According to variants of the invention, the shared contact comprises an integrated contact (which may be made of Tungsten W or Copper Cu) in at least said rear plane or contacts integrated into said rear lines.

According to variants of the invention, the integrated circuit comprises at least one deep isolation region having a lower limit lower than the lower limit of said rear plane at the periphery of said rear plane or said rear lines, the region located between at least the nMOS transistor and at least the pMOS transistor having a shallow isolation region, with a lower limit less low than the low limit of said rear plane or said rear lines.

Thus, in the present invention, by shallow insulation is defined an insulation which has a depth less than the thickness of the layer of insulation added to that of the rear plane, making it possible not to destroy the continuity of the rear plane, in the region between an nMOS transistor and a pMOS transistor.

According to variants of the invention, the integrated circuit comprises several transistors connected to the same rear plane.

According to variants of the invention, the integrated circuit comprises a dielectric which may be of oxide, situated below said rear plane and in contact with the latter and making it possible to produce so-called 3D architectures at several levels.

This is achievable in particular in the context of a 3D-monolithic or 3D-sequential type integration, comprising the formation of low level metals, a dielectric deposit and then the formation of metal island (s). ) (by litho / dielectric etching / metal deposition). Said rear plane can cover the entire upper grid and part of the source or the drain. The overlap is relative to the projection of the surfaces, the surface of said rear plane is thus greater than that of the upper grid. The integrated circuit may also include at least one lower level having at least one transistor located below said dielectric located below said rear plane.

The subject of the invention is also a method of manufacturing an integrated circuit according to the invention, comprising:

- the production of sources, drains and gates of one or more nMOS transistors and one or more pMOS transistors;

- the creation of at least one rear plane or rear lines, buried above the substrate;

- making the source and drain contacts of one or more nMOS transistor (s) and one or more pMOS transistor (s);

- the realization of one or more shared contact (s) to contact the grids and the rear plane or the grids and the rear lines.

According to variants of the invention, the production of the sources, drains and grids of the transistors is followed:

- depositing an etching stop layer for the contacts (CESL layer) which may be nitride on the surface of said sources, drains and grids, and a dielectric layer;

- making the source and drain contacts;

- successive deposits of at least: an etching stop layer for the contacts (CESL) which may be nitride, an oxide layer, a resin layer;

- Etching operations of said deposited layers to define one or more shared contact openings opening onto at least part of said grids and on the rear plane or shared contact openings opening onto at least part of said grids and lines back ;

- Filling said opening (s) with at least one electrically conductive material to define said shared contact (s).

According to variants of the invention, the method comprises:

- the realization of the sources, drains and grids of the nMOS and pMOS transistors;

- making one or more contacts integrated into said rear plane or said rear lines and one or more primary openings in the layer of insulation buried above said one or more rear plane contacts integrated;

- the deposition of a layer (CESL) above the sources, drains, grids and in said primary opening;

- making the source and drain contacts;

- the realization of one or more shared contact (s) on the surface of said integrated contact (s).

According to variants of the invention, the method comprises the following steps:

- successive deposits of at least: an etching stop layer for the contacts (CESL) which may be nitride, an oxide layer, a resin layer;

- Etching operations of said deposited layers to define one or more shared contact openings opening to at least part of the grids and on the rear plane or shared contact openings opening to the grids and on the rear lines;

- Filling said opening (s) with at least one electrically conductive material, to define the shared contact (s).

According to variants of the invention, the method comprises:

- the creation of a rear plane or rear lines by implantation through a mask on the surface of the active layers of semiconductor material of the nMOS and pMOS transistors, followed by:

- the production of sources, drains and gates of at least the nMOS transistor and at least the pMOS transistor;

- making the source and drain contacts of at least the nMOS transistor and the pMOS transistor and;

- the realization of the shared contact (s) to contact the grid and the rear plane or the grids and the rear lines.

According to variants, the method comprises the production of a buried dielectric layer situated below said rear plane making it possible to perform 3D configurations.

The invention will be better understood and other advantages will appear on reading the description which follows given without limitation and thanks to the appended figures among which:

- Figure 1 illustrates the current performance as a function of the voltage obtained with a single gate transistor and with a double gate transistor according to known art;

- Figure 2 illustrates a configuration of a set of pMOS and nMOS transistors according to the prior art;

- Figures 3a to 3e highlight the simple grid and rear plane contacts in a set of pMOS and nMOS transistors according to the prior art;

- Figures 4a to 4e illustrate a first example of a set of pMOS and nMOS transistors according to the invention;

- Figures 5a to 5e illustrate a second example of a set of pMOS and nMOS transistors according to the invention;

- Figures 6a to 6j illustrate the steps of a first method of manufacturing an example circuit comprising a set of pMOS and nMOS transistors according to the invention;

- Figures 7a to 7k illustrate the steps of a second method of manufacturing an example circuit comprising a set of pMOS and nMOS transistors according to the invention;

- Figures 8a to 8e illustrate a fourth example of a set of pMOS and nMOS transistors according to the invention comprising buried rear lines;

- Figures 9a to 9e illustrate an example of a method of manufacturing an integrated circuit of the invention comprising buried rear lines;

- Figures 10a to 10e illustrate sectional view of an example of an integrated circuit of the invention comprising several levels integrated in 3D;

- Figure 11 illustrates an example of a set of nMOS and pMOS transistors in an integrated circuit according to the invention comprising a rear line offset from the grid so as not to overflow on the drain side;

- Figure 12 illustrates a sectional view of an exemplary integrated circuit of the invention comprising a rear line offset from the grid so as not to overflow the drain side;

- Figure 13 illustrates an example of a set of transistors in an integrated circuit of the invention comprising a source shared between two adjacent transistors of the same type;

- Figure 14 illustrates a sectional view of an example of an integrated circuit of the invention comprising a source shared between two adjacent transistors of the same type.

In general, the integrated circuit of the invention comprises:

at least one transistor of the nMOS type and one transistor of the pMOS type, advantageously rows of nMOS transistors and rows of pMOS transistors;

- a gate common to an nMOS transistor and to a pMOS transistor;

- a rear plane, which in certain variants may have a small lateral dimension and correspond to what is defined as a rear line in the present invention;

- a shared contact between said grid and said rear plane.

First example of an integrated circuit according to the invention:

The integrated circuit comprises on a semiconductor substrate which may be made of silicon, a row of nMOS transistors and a row of pMOS transistors. A so-called active region is defined, comprising a rear plane shown in FIG. 4a. An nMOS transistor has a gate common with a pMOS transistor. According to this example, the three grids circumscribed in the so-called rear plane region can be connected to the same potential.

More precisely and as illustrated by all of FIGS. 4a to 4e, this example of circuit comprises on the surface of a semiconductor substrate 100:

- a buried layer 101 (which may be optional) of doped semiconductor (which may for example have a thickness of the order of 100 nm);

- a box 201 of doped semiconductor material;

- a rear plane 200 of doped semiconductor material, the doping of the box can be opposite to that of the rear plane, so as to be able to isolate the latter electrically by a reverse biased diode (the doping rate can for example be of of the order of 10 ¹⁶ - 10 ¹⁸ at / cm ³ and which may have a thickness of the order of 20 nm;

- a dielectric layer which may be buried oxide 300, commonly called BOX (and which may for example be 25nm thick);

- a so-called active layer of semiconductor material 400 from which the Source and Drain are produced which may have a thickness of approximately 7 nm with generally an upper layer 401 which may be of siliciding (formation for example of NiSi);

- to develop the gates of the transistors: a gate metal 600 which may have a thickness of approximately 40 nm in thickness, gate oxides 501 and spacers 502;

- Source and Drain contacts 701 and 702;

- an etching stop layer (commonly called "CESL" for "Contact Etch Stop Layer" 800 for Source and Drain contacts

- an upper dielectric 900 which may be oxide.

All of Figures 4a (top view), 4b (sectional view a), 4c (sectional view b), 4d (sectional view 2: contacts 704 and 705 correspond to single contacts: grid gate contacts nMOS and pMOS transistors in a region other than the so-called active region 4e (view in section 1) make it possible to highlight the shared contact 703 common to the grid and to the rear plane. These figures also show, in particular FIG. integrated circuit comprises a shallow isolation STh between the transistor nMOS and the transistor pMOS produced between the two active layers of the transistors, above a continuity of the rear plane.

Second example of an integrated circuit according to the invention:

This example of an integrated circuit is close to the first aforementioned example and also comprises so-called deep STI ₂ insulations (which may have a thickness greater than or equal to the thickness of the BOX layer + the thickness of the rear plane) at the periphery of the plane rear as illustrated by Figures 5a to 5e. The same references for designating the same elements are used identical to those of FIGS. 4a to 4e.

All of Figures 5a (top view), 5b (sectional view a), 5c (sectional view b), 5d (sectional view 2), 5e (sectional view 1) are used to highlight the contact 703 shared common to the grille and to the rear plane. These figures also show, in particular FIGS. 5a and 5e, that the integrated circuit comprises a shallow isolation STh between the transistor nMOS and the transistor pMOS produced between the two active layers of the transistors, above a continuity of the rear plane, and deep STI ₂ insulation on the periphery. The advantage of this example is that the rear planes are isolated laterally by the deep STIs ₂ and not by diodes (as in the previous example); which improves the insulation and widens the possible polarization ranges.

First example of a method of manufacturing a circuit according to a first example of a circuit of the invention described above:

The method, the main steps of which are written below, has a configuration illustrated in particular by the section views a and b, represented in FIG. 6a, and taking up the views illustrated in FIG. 4b and in FIG. 4c.

In a known manner, a silicon substrate is produced:

- isolations (STI or mesa) illustrated in Figure 6a;

- channel, rear plane 200 and box 201 layouts on the surface of a layer 101;

- the grid structure with metal 600;

- sources and drains in layers 401;

- the source 701 and drain 702 contacts on the active area;

- the deposition of a layer of dielectric 900.

Next, a nitride 801 deposit and an oxide deposit 901 are carried out, followed by a resin deposit 1000 in which etching patterns are produced by photolithography operations as illustrated in FIG. 6b.

Next, a new deposit of resin 1001 and local etching operations of the layers 801 and 901 are carried out as illustrated in FIG. 6c.

We then proceed to a local etching operation of the oxide layer 900, located above the grids 600, as illustrated in FIG. 6d.

Next, the nitride layer 801 is etched, as illustrated in FIG. 6e.

The resin layer 1001 is then removed by etching, as illustrated in FIG. 6f.

A new local etching operation is then carried out on the upper dielectric layer 900 to define the imprint of the shared contacts as illustrated in FIG. 6g.

We then proceed to a local etching operation of the nitride layer 800 at the grids, as illustrated in FIG. 6h. It should be noted that the thickness of the upper layer 801 of nitride is greater than the thickness of the lower layer 800 of nitride.

Then the etching of the buried oxide layer BOX, 300 is also carried out to finalize the opening intended for producing the shared contact, as illustrated in FIG. 6i. It is marked with an arrow, an oxide over-etching zone above the source / drain, this over-etching being to be minimized because it is harmful.

Finally, the shared contacts are made by filling the openings, for example with tungsten, followed by a CMP type operation (mechanical and chemical polishing operation) to finalize said contacts, as illustrated in FIG. 6j. The source and drain contacts 701, 702 and the shared grid and rear plane contacts 703 are thus obtained.

Second example of a process for manufacturing a circuit according to the invention

The first steps are identical to the first process steps described in the first example process, i.e. the steps recalled below:

In a known manner, using a silicon substrate 100:

- isolations (STI or mesa);

- channel layouts, rear plane 200 and box 201, on the surface of a layer 101;

- the grid structure with metal 600.

Then we proceed with the deposition of a layer of resin 1000, and a photo / etching operation to define upstream openings intended for shared contacts (grid / back plane), as illustrated in FIG. 7a, which illustrates the sections a and b of the structure described here.

An etching operation of the resin 1000 is then carried out, and an operation for example of siliciding 401 (formation, for example of NiSi) intended to define the source and drain contacts and integrated contacts 401c intended to form part of the contacts shared, as shown in Figure 7b.

The etching stop layer 800 may be made of nitride (CESL layer), as shown in FIG. 7c.

We then proceed to deposit a dielectric layer 900, an upper layer to define a hard mask 801 which may be made of nitride, an upper layer 901 of oxide and a resin 1001 followed by an operation of etching of the resin, as illustrated in Figure 7d.

An etching operation is then carried out on the layers of nitride 801 and on oxide 901, then on the etching of the resin 1001, on a new deposition of resin 1002 and on an etching of this new resin layer as illustrated in FIG. 7e .

An etching operation is then carried out in the dielectric layer 900, to carry out an intermediate step necessary to define upper openings intended for the shared contacts as illustrated in FIG. 7f.

An etching operation is then carried out on the upper layer of nitride 801 as illustrated in FIG. 7g.

A new etching operation is then carried out on the resin layer 1002 as illustrated in FIG. 7h.

Then a local dielectric 900 etching operation is carried out as illustrated in FIG. 7i.

One then proceeds to a local removal operation of the first layer of nitride 800 to produce the openings intended for producing the shared contacts, as illustrated in FIG. 7j.

We then carry out the drain / source contacts 701, 702 and shared contacts 703 (grid / rear plane comprising previously developed connection elements) by filling the openings with a metal which may be W, as illustrated in FIG. 7k.

Third example of a circuit according to the invention comprising buried rear lines and which can advantageously be integrated into a 3D architecture:

The circuit comprises a set of rear lines 200, facing the shared grids as illustrated by FIGS. 8a to 8e which respectively show a top view, a section a, a section b, a section 2 and a section 1.

Contacts 704 and 705 correspond to simple contacts: gate contacts of nMOS and pMOS transistors in a region other than the so-called active region. Figures 8c (section b) and 8e (sectional view 1) highlight the contact 703 common to the grid and to the rear plane. These figures also show, in particular FIG. 8e, that the integrated circuit comprises a shallow isolation STh between the transistor nMOS and the transistor pMOS produced between the two active layers of the transistors, above a continuity of the rear plane.

Example of a process for manufacturing a circuit according to the invention comprising buried rear lines:

It is also possible to produce rear lines buried in a semiconductor material as illustrated in FIGS. 9a to 9e.

On the surface of a substrate 100, a buried layer 101 (which may be optional) of doped semiconductor is produced and a box 201 of doped semiconductor material and a layer of buried oxide BOX, 300 under a thin layer of semiconductor material 400, as illustrated in FIG. 9a.

We just deposit and etch a layer of resin 1000 intended to make an implantation mask, as illustrated in FIG. 9b.

We then proceed to an implantation operation in order to define localized rear lines 200 as illustrated in FIG. 9c.

We can then proceed to the same steps as those described by in the first manufacturing process of the first example circuit of the invention. Shared contacts 703 are thus obtained which come into contact with the buried rear lines 200 as illustrated in FIG. 9d.

FIG. 9e is a top view showing all of the so-called active regions comprising shared contacts with buried rear lines.

The circuit of the invention can advantageously include a 3D integration of several levels of nMOS and pMOS transistors with rear planes or lines integrated in dielectrics which may be oxides (and not integrated in semiconductor materials with adapted dopings as previously described).

Example of a process for manufacturing a circuit according to the invention comprising rear lines buried in a 3D architecture:

It is also possible to produce rear lines buried in a dielectric material as illustrated in FIGS. 10a to 10e which show different sections of examples of 3D architecture.

FIG. 10a shows a first example in which a dielectric 300 is located below the rear lines 200.

In this example the lower E.l. includes nMOS and pMOS transistors corresponding to the examples described above. It should be noted that there may be one or more metal lines at the intermediate central level, the E.l. could include any other configuration.

To achieve this type of configuration, on the surface of a dielectric material 300 (possibly covering metallic interconnection lines), a doped semiconductor material or a metal is deposited. We just deposit and engrave a resin layer intended to make a mask. An etching operation is then carried out in order to define rear lines 200 located as illustrated in FIG. 10a.

Alternatively, the rear lines can be produced by a damascene process (known per se) which consists in producing cavities in the dielectric, in depositing the metal in a non-selective manner then in carrying out a mechanical-chemical planarization operation to remove the metal outside the cavities. We can then deposit a dielectric and a semiconductor layer (for example Si), for example by plate bonding (wafer bonding), as described in 3D-sequential integration (Brunet et al, VLSI’17).

We can then proceed to the same steps as those described by in the first manufacturing process of the first example circuit of the invention. Shared contacts 703 are thus obtained which come into contact with the buried rear lines 200.

Figures 10b to 10e show different sections a, b, 2 and 1 (relating to the same sections as those of all of the previous figures) of another example of 3D configuration with a rear plane in dielectric 300, the lower part El which may be identical to that illustrated in FIG. 10a.

Fourth example of a circuit according to the invention comprising eccentric buried rear lines

It may be particularly interesting to define a configuration in which the buried rear lines do not project (in vertical projection) relative to the front gates on the drain side of the nMOS and pMOS transistors as illustrated in FIG. 11 which highlights a pMOS transistor, a nMOS transistor, with the sources of the transistors referenced S and the drains of the transistors referenced D. A common rear line 200 is positioned opposite the central gate 600 in an off-center manner on the source side, thus not overflowing on the drain side.

The fact of not overflowing the rear line on the side of the drains of the transistors makes it possible to reduce the stray capacitances between the rear line and the drain and therefore improves the dynamic performance of the circuits.

Overflows on the drain side are more disadvantageous than on the source side in dynamic performance.

Advantageously, it is therefore preferred not to have an overflow from the rear line on the drain side.

In a 3D architecture with a lower part E.l. as mentioned previously, this type of configuration can also be produced having off-center rear lines and not projecting (in vertical projection) relative to the front gates on the drain side of the nMOS and pMOS transistors, as illustrated in FIG. 12 which highlights the shared contact 703 and the rear line 200 located below an insulation layer 301 and offset from the upper grid 600.

Fifth example of a circuit according to the invention comprising common sources between two adjacent transistors:

According to this example, the circuit of the invention comprises a common source between two adjacent nMOS transistors and a common source between two adjacent pMOS transistors.

FIG. 13 illustrates a configuration advantageously having a central common source S between 2 transistors of the same type and a rear line 200 which is superimposed (in vertical projection) on the front gates

600 and at the common source S with two adjacent transistors of the same type. Drains D are represented by and from other central sources S.

In a 3D architecture with a lower part E.l. as mentioned above, this type of configuration can also be produced with a rear offset line and not projecting (in vertical projection) relative to the front gates on the drain side of the nMOS and pMOS transistors and a source shared between two transistors of the same type as illustrated in FIG. 14 which highlights the shared contact 703 contacting the rear line 200 situated below an insulation layer 10 301 and the front grid 600.

Claims (19)

1. Integrated circuit comprising: - a substrate; - a layer of buried insulation; - at least one nMOS transistor comprising a layer of semiconductor material disposed above said layer of buried insulator; - at least one pMOS transistor comprising a layer of semiconductor material disposed above said layer of buried insulator; - at least one semiconductor rear plane that can be doped or metallic disposed above the substrate and below the buried insulating layer, said buried plane being common to said nMOS transistor and to said pMOS transistor; at least one gate insulator and one gate common to said nMOS transistor and to said pMOS transistor and situated above the channel of these transistors and opposite said rear plane, the surface of the rear plane covering at least the surface of the grid in vertical projection ; said nMOS transistor being separated from said pMOS transistor by an insulation defined between said layer of semiconductor material of said nMOS transistor and said layer of semiconductor material of said pMOS transistor, said insulation being located in said layer of buried insulator and in contact with said rear plane; - At least one shared contact electrically contacting said common grid and said common rear plane, said shared contact passing through the buried insulating layer or said insulation. 2. Integrated circuit according to claim 1, in which said shared contact is located between said nMOS transistor and said pMOS transistor. 3. Integrated circuit according to one of claims 1 or 2, in which the buried plane is defined in a doped semiconductor region called a well, of the type opposite to that of said rear plane, said rear plane being doped semiconductor. 4. Integrated circuit according to one of claims 1 to 3, comprising several nMOS transistors, several pMOS transistors, common rear lines between an nMOS transistor and a pMOS transistor, said rear lines being opposite said common gates and being separated by a dielectric. 5. Integrated circuit according to claim 4, comprising rear lines which do not project in vertical projection with respect to said gates of said nMOS and pMOS transistors on the side of the drains of said nMOS and pMOS transistors. 6. An integrated circuit according to claim 5, comprising rear lines offset from the source side of said transistors with respect to said gates of said nMOS and pMOS transistors so as not to be facing the drains of said nMOS and pMOS transistors. 7. Integrated circuit according to one of claims 1 to 6, comprising at least two adjacent nMOS transistors and at least two adjacent pMOS transistors, said adjacent nMOS transistors and said adjacent pMOS transistors having a common source between transistors of the same type and a line. common rear which is superimposed in vertical projection on the gates of the two said nMOS and pMOS transistors and on the common source. 8. Integrated circuit according to one of claims 1 to 7, in which the shared contact comprises a contact integrated in at least said rear plane or contacts integrated in said rear lines, which may be made of Tungsten or Copper. 9. Integrated circuit according to one of claims 1 to 8, comprising at least one deep isolation region having a lower limit lower than the lower limit of said rear plane at the periphery of said rear plane or said rear lines, the region located between at least the nMOS transistor and at least the pMOS transistor having a shallow isolation region, with a lower limit less low than the low limit of said rear plane or said rear lines. 10. Integrated circuit according to one of claims 1 to 9, comprising several transistors connected to the same rear plane. 11. Integrated circuit according to one of claims 1 or 10, comprising a dielectric which may be oxide, located below said rear plane. 12. An integrated circuit according to claim 11, wherein said rear plane covers the whole of the upper grid and part of the source or the drain. 13. An integrated circuit according to claim 12, comprising at least one lower level having at least one transistor located below said dielectric located below said rear plane. 14. Method for manufacturing an integrated circuit according to one of claims 1 to 13, comprising: - the production of sources, drains and gates of one or more nMOS transistors and one or more pMOS transistors; - the creation of at least one rear plane or rear lines, buried above the substrate; - making the source and drain contacts of at least the nMOS transistor and at least the pMOS transistor; - the realization of one or more shared contact (s) to contact the grids and the rear plane or the grids and the rear lines. 15. The manufacturing method according to claim 14, in which the production of the sources, drains and gates of the transistors is followed: - the deposition of an etching stop layer for the contacts (CESL layer) which may be made of nitride on the surface of said sources, drains and grids, and of a layer of oxide dielectric; - making the source and drain contacts; - successive deposits of at least: an etching stop layer for the contacts (CESL) which may be nitride, an oxide layer, a resin layer; - Etching operations of said deposited layers to define one or more shared contact openings opening onto at least part of said grids and on the rear plane or shared contact openings opening onto at least part of said grids and lines back ; - Filling said opening (s) with at least one electrically conductive material to define said contact (s) shared. 16. Method for manufacturing an integrated circuit according to one of claims 14 to 15, comprising: - the realization of the sources, drains and grids of the nMOS and pMOS transistors; - making one or more contacts integrated into said rear plane or said rear lines and one or more primary openings in the layer of insulation buried above said one or more rear plane contacts integrated; - the deposition of a layer (CESL) above the sources, drains, grids and in said primary opening; - making the source and drain contacts; - The realization of shared contact (s) on the surface of said integrated contact (s). 17. The manufacturing method according to claim 16, comprising the following steps: - successive deposits of at least: an etching stop layer for the contacts (CESL) which may be nitride, an oxide layer, a resin layer; - Etching operations of said deposited layers to define at least one shared contact opening opening on at least part of said grid and on the rear plane or shared contact openings opening on the grids and on the rear lines; - Filling said opening (s) with at least one electrically conductive material, to define the shared contact (s). 18. The manufacturing method according to claim 16, comprising: - the creation of a rear plane or rear lines by implantation through a mask on the surface of the active layers of semiconductor material of the nMOS and pMOS transistors, followed by the steps of: - the production of sources, drains and gates of at least the nMOS transistor and at least the pMOS transistor; - making the source and drain contacts of at least the nMOS transistor and the pMOS transistor; - the realization of the shared contact (s) to contact the grid and the rear plane or the grids and the rear lines. 19. The manufacturing method according to one of claims 14 to 18, comprising the production of a buried dielectric layer located below said rear plane.