FR3051575A1 - ERASING MANAGEMENT IN A FLASH MEMORY - Google Patents

Abstract

The invention relates to a method for managing a flash memory, wherein: the memory is organized in pages (P1); and each page contains a metadata word (PMD1 (6)) for storing a number of deletions of the page.

Description

ERASING MANAGEMENT IN A FLASH MEMORY

Field

The present description generally relates to electronic circuits and, more particularly, circuits using a flash memory. The present description aims more particularly at managing a flash memory.

Presentation of the prior art

Flash memories are increasingly used in microcontrollers for nonvolatile storage of information.

The storage of data in a flash memory presents various temporal constraints related to the granularity of the operations carried out, the writing being carried out by word (for example, by word of four bytes) while the erasure is carried out by page of several words (a few tens to a few hundred words).

In certain applications, it is desired to ensure that the transactions carried out and stored comply with an atomicity criterion. The atomicity of a transaction is to ensure that data stored in memory has an exploitable state and integrity. This is to ensure that data in non-volatile memory have either the state before the transaction or the state after the transaction concerned but they do not have an intermediate state.

Transaction Atomicity Management is particularly used in applications where an interruption of circuit power or the occurrence of accidental or deliberate disruption can result in the storage of data in a state rendering it unusable thereafter are vulnerable to the point of confidentiality or their integrity. For example, in the field of microcircuit cards, it is desired to ensure that in case of accidental or accidental tearing of a card of the reader in which it is located, the information contained in a flash memory of the map are reliable. In a circuit incorporating a security module, the equivalent of the tearing out corresponds to a power failure of the circuit. summary

There is a need to improve the management of information storage in flash memory, particularly to preserve the atomic character of certain transactions involving a data update in the flash memory.

One embodiment overcomes all or part of the disadvantages of known techniques for managing a flash memory.

An embodiment of a first aspect facilitates atomicity management of transactions in a flash memory.

An embodiment of a second aspect balances the deletion of the pages of a flash memory.

Thus, an embodiment of the first aspect provides a method for managing a flash memory, wherein: the data to be stored is organized into logical blocks; the memory is divided into pages / each page is divided into frames, each frame may contain at least one data block and at least two frame metadata words / each page has at least one page metadata word which contains, when a page is written, a value of a count of the number of pages written / a writing of a logical block in the memory is accompanied by a programming of a first frame metadata word with an identifier of this logical block ; and the page in which to write is selected as the one whose first metadata word contains the maximum value of the page counter written among all the pages.

According to one embodiment, the frames are written sequentially in a page.

According to one embodiment, the first frame metadata word also contains a value representative of an error control code calculated at least from the data block of the frame.

According to one embodiment, when writing a frame, a second frame metadata word is written first with a value, independent of the content of the data to be written and which is always the same for a given frame.

According to one embodiment, said second metadata word has a fixed value for all the frames of the memory.

According to one embodiment, said first page metadata word is written before writing a first frame in the page.

According to one embodiment, a reading of a logical data block comprises the steps of: searching for the last written frame whose block identifier corresponds to that of the logical block; check that the writing of the data in the latter frame respects an error control code and, if it is not the case, search the previous written frame whose block identifier corresponds to that of the logical data block up to 'to have gone through all the pages.

According to one embodiment, a memory management circuit performs, at each start, an atomicity check of the last written frame.

According to one embodiment, in case of atomicity defect, all the valid frames of the current page are transferred to an available page and the current page is erased.

According to one embodiment, said available page is a dedicated page.

An embodiment of this first aspect also provides a flash memory, programmed according to the above method.

An embodiment of this first aspect also provides an electronic circuit comprising a flash memory.

An embodiment of the second aspect provides a method of managing a flash memory, wherein: the memory is organized into pages; and each page contains a metadata word for storing a number of deletions of the page.

According to one embodiment, the selection of a page to be erased to free space is effected according to the number of erasures suffered by the different pages in order to standardize the number of erasure suffered by each page.

According to one embodiment: the data to be stored are organized in logical blocks; the memory is divided into pages; each page is divided into frames, each frame may contain at least one data block and at least two frame metadata words; each page has at least one page metadata word which contains, when a page is written, a value of a counter of the number of pages written; a writing of a logic block in the memory is accompanied by a programming of a first frame metadata word with an identifier of this logical block / and the page in which to write is chosen as the one of which the first metadata word contains the maximum value of the page counter written among all the pages.

An embodiment of this second aspect also provides a flash memory, programmed according to the above method.

An embodiment of this second aspect also provides an electronic circuit comprising a flash memory as above.

Brief description of the drawings

These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures in which: FIG. 1 is very schematically and in form blocks, an embodiment of an electronic circuit of the type to which apply, by way of example, the embodiments that will be described; FIG. 2 illustrates an embodiment of a logical organization of data to be stored in a flash memory; FIG. 3 illustrates an embodiment of a physical organization of data in a flash memory; FIG. 4 very schematically illustrates an embodiment of a frame structure of the memory of FIG. 3; FIG. 5 is a block diagram illustrating an embodiment of a writing of a piece of data in FIG. The memory / FIG. 6 is a block diagram illustrating an embodiment of a preparation of a next page for writing when a current page is full. FIG. 7 is a block diagram illustrating an embodiment of a block. reading a data in the memory; Fig. 8 is a block diagram illustrating an embodiment of page-level atomic recovery; and Fig. 9 is a block diagram illustrating an embodiment of selecting a page to be erased according to the second aspect.

detailed description

The same elements have been designated with the same references in the various figures.

For the sake of clarity, only the steps and elements useful for understanding the embodiments that will be described have been shown and will be detailed. In particular, the electrical operation of a flash memory during the steps of writing, reading and erasing has not been detailed, the embodiments described being compatible with the usual technologies of flash memories. In addition, the applications using atomicity management have also not been detailed, the embodiments described being, again, compatible with the usual applications.

FIG. 1 very schematically shows in the form of blocks an embodiment of an electronic circuit 1 of the type to which, by way of example, the embodiments which will be described will be applied.

The circuit 1 comprises: a processing unit 11 (PU), for example a state machine, a microprocessor, a programmable logic circuit, etc. ; one or more volatile storage areas 12 (RAM), for example of the RAM or registers type, for temporarily storing information (instructions, addresses, data) during the processes / one or more non-volatile storage areas, of which at least one flash memory 2 (FLASH) for storing information in a durable manner and in particular when the circuit is not powered; one or more buses 14 of data, addresses and / or commands between the various elements internal to the circuit 1; and an input-output interface (I / O) for communication, for example of the serial bus type, with the outside of the circuit 1.

If necessary, the circuit 1 also integrates a contactless communication circuit 16 (CLF - ContactLess Front-end), Near Field Communication (NFC) type.

Furthermore, the circuit 1 can integrate other functions, symbolized by a block 17 (FCT), depending on the application, for example, a crypto-processor, other interfaces, other memories, etc.

The management of the atomicity of transactions in a circuit equipped with a flash memory is particular because the flash memory does not have the same processing granularity depending on the type of operation. In particular, the writing is done by word (one byte or a few bytes) while the erasure is per page. The size of a word generally corresponds to the size of a register receiving the serial data to transfer them in parallel to the write memory plane. A page is defined as the minimum size that can be addressed simultaneously for deletion. Typically, a page represents, in a flash memory, 64, 128, 256, 512 or 1024 bytes.

A flash memory is programmed, from an initial state, designated arbitrarily 1, to states 0 (non-conductive states of the cells). This means that the cells of the memory must be initialized to a high state (erasure) and that, to store data (write), one intervenes (programming with 0) or not (state of the bit with 1) on the states of the bits by data word.

In order to guarantee the atomicity of the transactions, the flash storage of a piece of data must only be considered valid once the transaction is over and the data is said to be stable. In practice, the atomicity management methods activate a data processing indicator when it is extracted from the non-volatile memory, then organize the storage of the updated data, once the processing is completed, the processing indicator then changing state. Atomicity can concern a larger or smaller amount of data depending on the nature of the transaction.

The atomic character of the transactions is particularly important in the case of bank-type transactions (payment for example) where it is necessary to ensure that the information stored in the flash memory, for example the balance of an electronic purse or an authorization to purchase, or the identifier validating a transaction, is stored reliably. Generally to guarantee the atomicity of a transaction, atomic temporary storage spaces (Buffer) are used which are updated with the initial information, then final, for transfer to the main non-volatile memory.

However, in the case of a flash memory, a difficulty lies in the erase procedure because of its page granularity which is relatively long compared to the word write operation. In particular, there is a need to indicate that an erased page is stable, i.e. it has been able to be erased completely. Otherwise, a weakness in data security is introduced. Moreover, if it is necessary to erase a page with data transfer in a new page, this transfer can make stable data present in the page to be erased unstable. This occurs especially with large pages (for example of the order of a hundred words or more) because they are more likely to contain old data considered stable and must be transferred to a new page .

In contactless applications, the transactions must be carried out very quickly because of the fleeting nature of the communication which is related to the duration during which the circuit 1 can communicate with a terminal. However, managing the atomicity of transactions using buffers in flash memory takes time, because of the erasure operations that are necessary to allow programming.

According to the embodiments which will be described, provision is made to organize in a particular manner the storage of the data in the memory.

Figure 2 illustrates an embodiment of a logical data organization to be stored in a flash memory. In other words, this figure illustrates how the data are managed by the processing unit 11 and the different entities of the circuit 1 of FIG. 1 for storage in the flash memory. Reference is made thereafter to a memory management circuit responsible for organizing its addressing, writing, reading and erasure as well as the conversion of logical addresses into physical addresses. This circuit or management unit is a circuit programmed according to the implementation of the method described and is optionally the processing unit.

According to this embodiment, the set of data representing the storage capacity of the flash memory is seen as a single 2V network of block data B1, B2, etc. and each block Bi contains the same number of words W. In the example shown in FIG. 2, it is assumed that each block of data Bi contains four words W1, W2, W3 and W4. The size of a word corresponds to the writing granularity in the flash memory, in practice from one to a few bytes (for example four). However, this is an arbitrary example and any other number of one or more bytes may constitute a word and any other number of one or more words may constitute a block. Thus, the logical division of the flash memory is not performed per page but by block B whose size is independent of the size of the pages.

A data A to be stored in the memory 2 comprises an arbitrary number of bytes, independent of the size of a block. From a logical point of view, that is to say for the processing unit 11, a datum is defined by a length L (A), that is to say a number of bytes and its position. in the 2V network of blocks Bi by an offset 0 (A), that is to say an offset from the beginning of the network 2V.

Figure 3 illustrates an embodiment of a physical organization of data in a flash memory.

The transition between the logical organization (FIG. 2) and the physical organization of the data storage is transparent for the processing unit 11 and the other circuits accessing the memory. The memory management unit 2 converts virtual addresses provided by the different entities into physical addresses. Moreover, to manage the atomicity, the management unit generates metadata which are also stored in the memory 2.

In order to respect the erasure constraint, the memory is physically organized into pages P, representing the erasure granularity. The memory is therefore divided into r pages P of identical sizes. Each page has the same number of words, constituting the writing (and reading) granularity. The pages are preferably divided into two categories.

A first category comprises pages PI divided into n frames Fj each having several data words (set DBj) and the same number of words FMDj frame metadata (from one to a few, for example two). For example, all frames have the same number of data words. Each page PI further comprises a number m (a few to a few tens) of page metadata words PMD1 (k) independent of the frames. The number of data words of each frame preferably corresponds to an integer multiple (at least 1) of the number of data words of each DB block of the virtual organization of the memory. Thus, a frame Fj contains a DBj data block and EMDj frame metadata. In FIG. 3, for each frame, the DBj block followed by the FMDj metadata is illustrated. However, preferably and as will be seen later, part of the metadata is written at the beginning of the frame Fj.

A second category of pages, in a much smaller number than the number of pages PI of the first category, contains only memory metadata words MMDh.

Preferably, the second category has only one page Pr and the first category therefore comprises r-1 pages PI.

Alternatively, only pages of the first category are provided.

According to a particular embodiment, a page contains 1024 bytes. It is expected that r-1 PI pages of the first category will each contain 25 frames of 10 words each and 6 words of page PMD1 metadata. Each frame Fj contains a DBj block, eight W words of data, and two FMDj frame metadata words. According to this particular embodiment, each frame can therefore contain two logical blocks Bi. Moreover, a single page Pr of MMDh words of memory metadata is provided.

This is a particular example and other granularities may be provided as long as all the words are the same size, representing the writing granularity in the memory. In particular, it is possible to provide logical blocks Bi of variable size (number of words) which are then capable of being distributed in several DBj blocks in several frames.

The FMDj frame metadata contain at least one word FCONST (preferably a single word FMDj (1)) of fixed value, identical regardless of the value of the data contained in the DBj block and at least one word (preferably a single word FMDj (2)) containing the number or numbers (identifier (s) i) of the virtual block (s) Bi written in the real block DBj. The word EMDj (2) also contains a status indicator FW (end of writing) of the DBj block and an error control code of CRC type, signature or other. The frame metadata is used for the frame atomicity, i.e. whether the DBj block contained in the frame is stable or not.

FIG. 4 very schematically illustrates one embodiment of a frame structure Fj assuming two metadata words EMDj.

According to this embodiment, the metadata word EMDj (1) of fixed value FCONST is first written, then the words of the data A and finally the metadata word FMDj (2). The CRC code contained in the word EMDj (2) is preferably a CRC of the word EMDj (1) and the block DBj. Thanks to the use of a fixed value for the word EMDj (1), we will be able to ensure that there was no tearing or attack at the beginning of the writing of the frame, for example an attempt to modify the content of the DBj block during an attack. The value is fixed, that is to say the same for a given frame, but can vary from one frame to another. Preferably, for convenience, the value is the same for all the frames of the memory.

According to the first aspect, the PMD1 page metadata contains a word PMD1 (l) indicating that the page has begun to be written and that it is no longer blank, preferably but optionally a word PMD1 (2) indicating that the page is full, a word PMDl (3) indicating that the next page is erased (therefore blank), a word PMDl (4) indicating that the page is obsolete, that is to say that none of the frames contains a block still useful (in other words, that all the blocks of this page have already been modified in other pages later) and a word PMDl (5) containing a sequence number of the page, that is, ie the value of a PWN counter of the number of pages written. The page metadata according to this first aspect is used to indicate the switchover from one page to another and to allow an atomicity recovery at start or reset of the circuit. The words are not necessarily physically in this order on the page.

According to the second aspect of the description, the page metadata furthermore contains, or instead of the word PMD1 (3) indicating that the page has been erased, a word PMD (6) indicating the number of erasures that has occurred. the page.

The only link between logical sizes and the physical organization of memory is that all words are the same size. Remember that when a word is blank (erased), all bits are in a first state (designated high or 1). The programming of a word to store a value consists in selecting the bits of the bytes of the word that must change state and be written (switch to the low state or 0). The programming of a flag or indicator consists in programming the bit or bits of the byte in the state corresponding to the low state. It is also recalled that once written or programmed in state 0, the contents of the word can not be modified except to erase the whole page and reprogram it. The writing of the data in the memory is carried out block by block as and when they are received and successively in each page. Thus, in case of successive writes of the same logical block (for example, the value of a counter), this same block of data Bi can be found written several times in the memory with different values as and when writings. This contributes to the resolution of the atomicity problem insofar as, from the moment when a datum A has been written once with a first value, it will always be possible, when writing later, to return to the previous value representing the Steady state if there is a problem writing the current value.

On the other hand, on the 2V logical memory side, the same data A is always "stored" in the same block Bi (or the same blocks). Thus, the identifier i (the address) of the block Bi in the logical memory makes it possible to retrieve the physical block or blocks DBj of the memory 2 containing the data item A (containing the successive values of the data item A).

For simplicity, the operation is subsequently explained by arbitrarily assuming that the data item A considered is one and only one block Bi and that the blocks DBj are the size of a block Bi. However, all that is described applies more generally to the practical case where a data A can occupy several blocks or a block portion and at different sizes of the blocks Bi and DBj.

FIG. 5 is a block diagram illustrating an embodiment of a writing of a data item A in the memory 2. From the length L (A) and the offset 0 (A) of the data item A in FIG. 2V virtual network (Figure 2), the memory management circuit determines (block 51, i = f (L (A), 0 (A))) the identifier i DBi block containing this data.

Then, the page PI with the highest number of PWNs written pages is selected (block 52, SELECT 1 (MAX (PWN)) by browsing (by reading) the corresponding words PMD1 (5) of the page metadata.

Then, (block 53, SELECT j) is identified, the first frame Fj available sequentially in the page PI. This selection is made, for example, by traversing the frames successively to the first of which the word EMDj (1) for the fixed value FCONST is not programmed. As a variant, the second metadata word EMDj (2) is read and the first frame whose end writing flag EW FMDj is in the state 1 or whose block identifier i is not programmed is selected. . It is assumed in this example that a new page is opened at the end of the writing of the last frame of a page. Therefore there is inevitably a frame available in step 53.

Alternatively, if no frame is free, it means that the page is full. We then run a subroutine to open a new page. This subroutine will be explained later in connection with FIG.

Once the frame Fj is selected, it starts by writing (block 54, FCONST -> EMDj (1)), in the frame Fj, the first word FMDj (1) fixed metadata (it is actually the first word written logically.Physically, the words can be in a different order in the frame). Then write (block 55, A -> DBj) the data A in the block DBj, then write (block 56, (i, FW, CRC) -> EMDj (2)) the second word EMDj (2) of metadata with the identifier i, the FW end of writing indicator and the CRC of the first words (BMDj (1) and DBj) of the frame.

We then check if the page is full, that is to say if there is a frame Fj available for the next write (block 57, EXIST NEXT j?). In the affirmative (output Y of block 57), the writing is finished (block 58, END). In the case where a data item A can represent several DBi blocks, step 53 is returned to write in the next frame. In a more general case where the frames are of variable size and where the space available at the end of the page is not sufficient to store the following frame, either leave a blank space or cut the frame in two and stores a portion on the current page and a portion on the next page.

In the negative (output N of block 57), that is to say if there is no more frame available, prepare a next page for the next write (block 6, NEXT 1). To simplify, we consider the case where we prepare the next page (index 1 incremented by one unit) but we can more generally expect to link several pages together to speed up the writing speed of several blocks without intermediate erasure . In this case, it is planned to skip one or more pages when a page is full.

Fig. 6 is a block diagram illustrating an embodiment of a preparation of a next page for writing when a current page is full.

We start (block 61, 1 -> PMD1 (2)) by closing the current page, that is to say by programming its metadata word PMD1 (2) end of page or full page. Then (block 62, SELECT NEXT 1), we select the next page PI available, that is to say, obsolete. The value of the number of pages written, incremented by 1, is then programmed (block 63, PWN + 1 -> PMD1 (5)) in the corresponding word PMD1 (5) of page metadata and is also programmed (block 64, 1 -> PMDl (l)) the page open indicator.

With such a process of writing in the memory 2, one is able, in reading, to find the last atomic transaction for each data.

FIG. 7 illustrates, in block diagram form, an embodiment of a reading of a data item A in the memory 2. From the length L (A) and the offset 0 (A) of the data A in the virtual network 2V, the memory management circuit determines (block 71, i = f (L (A), 0 (A))) the identifier i of the block Bi containing this data item. The reading in the memory is performed by browsing the frames Fj from the last written frame of the last page written by searching in which DBj block is the block Bi, by its identifier i. In practice, one goes through (block 72, SEARCH i in FMDj (2)), by going up memory 2 from the page having the highest number of PWN written pages in its metadata word PMD1 (5) and, per page, since the last written frame of the page. We stop at the first occurrence of the identifier i in a second word FMDj (2) of frame metadata.

Once the frame has been found, it then checks (block 73, FW OK?) The status indicator FW which indicates whether the writing of the frame has ended without tearing indicating, in principle, whether the data are stable or not. no.

If the status indicator is not valid (output N of block 73), then the frames (block 72) are moved up to that containing the previous version of the DBj data block.

If the status indicator is valid (output Y of block 73), the error code is checked (block 74, CRC OK?) By recalculating a CRC on the data present in the first metadata word FMDj (1) and in the data block (DB (j)).

If the calculated code is identical to the stored code (output Y of the block 74), the data block DBj is valid and the reading provides (block 75, RETURN A = DBj) the value of the block DBj as the data A, so as content of the virtual block Bi.

If the CRC code is not confirmed (output N of block 74), it means that the data is unreliable. We then go back the memory (block 72) in order to find the previous writing of the data, which amounts to looking for the last atomic transaction.

In a variant, when a frame whose CRC is erroneous (output N of block 74) is identified, it is first written in the second metadata word FiynDj (2), an indicator that the frame is polluted. This saves a little time on the next reading of the data A because it avoids recalculating the CRC before going back to the previous occurrence.

Fig. 8 is a block diagram illustrating an embodiment of a page-level atomic recovery.

In practice, this process is performed at startup or during a reset of the circuit, which amounts to checking the atomicity after each accidental or voluntary tearing or extinguishing.

We first select (block 81, SELECT 1 (MAX (PWN)) the page having the maximum value of the counter of the number of pages written. Then, we select (block 82, SELECT j) the last frame written on this page. The second metadata word EMDj (2) is then read and it is verified (block 83, FW OK?) That the write flag FW is correct (is programmed). In the affirmative (output Y of block 83), there is no problem of atomicity and the cut or reset was carried out while the writing processes in the flash memory were finished. We then go to nominal operation, that is to say that the atomicity verification process is terminated (END). Alternatively, to ensure that there was no tearing at the end of writing and to ensure the stability of the word EMDj (2), reprogramming the same value in the word EMDj (2).

If not (output N of block 83), this means tearing (power failure or reset) while writing to the flash memory. According to a preferred embodiment, the page Pr is then used to transfer (block 84, TRANSFER DBj (PI) -> DBj '(Pr)) all the valid frames from the page PI to the page Pr. Then, we delete the PI page (block 85, ERASE PI). The different steps of the copy, to the page Pr and then the copy from the page Pr, are validated by metadata words in the page Pr to ensure that in case of tearing during the recovery procedure, the procedure started is continued well and we do not start again at the beginning of the tearing procedure at the risk of permanently losing the still valid data in the page PI.

According to one embodiment, the page Pr is a dedicated page of the memory. In this case, a reverse transfer (block 86, TRANSFER DBj '(Pr) -> DBj (PI)) of data stored temporarily in the page Pr to the deleted page PI is performed. The page metadata is then also rewritten. Finally, we delete the page Pr (block 87, ERASE Pr) so that it is ready for next use.

According to another embodiment, the page Pr is any available page. In this case, it is not necessary to transfer the data to the PI page after deletion.

Preferably, the processing of FIG. 8 also comprises a step of checking the atomicity of the page metadata. For this, it verifies, during a restart and on the last page written, an error correction code stored in one of the page metadata words PMDl (k).

Preferably, before step 84, the PMD1 (2) metadata words of all the pages that are written after the selected frame Fj in block 82 are written as indicating a full page. Thus, these pages can not be used without being erased.

According to the variant where only the pages of the first category are used, it is impossible to copy the reliable frames to a new page following the detection of an erroneous frame. Indeed, the problematic frame will in any case not be considered in reading and we will read the previous reliable data.

However, this reduces the capacity of the memory in terms of the number of tearing it can support as long as lost frames are kept.

The number of available pages (erased) is at least two in order to erase a page. When there is no more page available (other than the two minimum), one selects one of the written pages, preferably the page whose number of written frames is minimum. This page is then scanned to be erased by checking its frames and those of them which contain the last reliable states of blocks Bi. All of these blocks are transferred (written) as described in connection with Figure 4 to one of the available pages. Thus, at most n blocks are transferred (in practice, there are at least some frames that contain obsolete data so that this transfer results in frames available in this page). Once the transfer is complete, the original page is erased. After erasing, program the erased page indicator (PMD1 (4)).

As a variant, a minimum number of upper pages, for example three or four, is fixed so as to have more available frames in order to store a larger number of transactions without requiring an erasure.

According to the second aspect of the present description, each erasing of a page of the flash memory 2, increments a number of erasure counter of the page concerned.

FIG. 9 is a block diagram illustrating an embodiment of a selection of a page to be erased according to this second aspect.

To erase a page PI (ERASE Pl), we begin, as indicated above, to transfer (block 91, TRANSFER DBj (Pl) -> DBj '(Pl')) all the data blocks DBj of the page Pl whose content represents the last stable value of a data item to a block DBj '(Pl') of one of the available memory pages. The counter NPE of number of page erasures in a metadata word of the previous page is stored (block 92, TEMP NPE), then the page PI (block 93, ERASE PI) is deleted. Once the deletion has been carried out, the metadata word PMD1 (6) is programmed (block 94, NPE + 1 -> PMD1 (6)) to the value of the number of deletions incremented by one.

According to this embodiment, the selection of the page to be erased does not necessarily correspond to the page having the minimum value of the number of pages written but to that having the minimum value of pages written among the pages having undergone a smaller number of erasures. . The application of this embodiment makes it possible to optimize the lifetime of the flash memory by optimizing the homogeneity of the number of erasures among the number of pages. Indeed, if there was no atomic recovery process, the page having the maximum value of the number of pages written would be among those having been erased a lesser number of times. However, since the application of the page-level atomic recovery process results in a transfer, with the same value of the number of pages written to an available page, this does not necessarily correspond, especially in case of many implementations of atomic recovery.

Note that, if this second aspect can be combined with the first, it can also be implemented more generally in any method of managing a flash memory.

Another advantage is that in the case of implementation of the page-level atomic recovery process as described in connection with FIG. 9, there is a risk that the error is in the number of written pages, in which case this page risk, without the implementation of the number of erasure counter, never to be erased.

An advantage of the embodiments that have been described is that they improve the management of a flash memory for the processing of operations that must comply with an atomicity criterion.

Another advantage is that they easily make it possible to go back to the last atomic value of a datum.

Various embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. Furthermore, the practical implementation of the embodiments that have been described is within the abilities of those skilled in the art from the functional indications given above and using circuits in themselves usual. In particular, the organization of the addressing of the memory and the generation of the signals adapted to its control and to this addressing makes use of techniques that are in themselves usual.

Claims (5)

A method of managing a flash memory (2), wherein: the memory is organized into pages (PI); and each page contains a metadata word (PMD1 (6)) for storing a number of deletions of the page. 2. The method as claimed in claim 1, in which the selection of a page (PI) to be erased in order to free up space is effected according to the number of erasures suffered by the different pages in order to unify the number of pages. erasure suffered by each page. 3. Method according to claim 1 or 2, wherein: the data (A) to be stored are organized in logical blocks (Bi); the memory is divided into pages (PI); each page is divided into frames (Fj), each frame may contain at least one block (DBj) of data and at least two frame metadata words (FMDj); each page has at least one page metadata word (PMD) which contains, when a page is written, a value of a counter (PWN) of the number of pages written; a writing of a logic block in the memory is accompanied by a programming of a first frame metadata word (FMDj (2)) with an identifier (i) of this logical block; and the page in which to write is selected as the one whose first metadata word contains the maximum value of the page counter written among all the pages. Flash memory (2), programmed according to the method according to any one of claims 1 to 3. Electronic circuit (1) comprising a flash memory (2) according to claim 4.