FR3050573A1 - DEVICE WITH SEGMENTED FIELD PLATES - Google Patents

Abstract

The invention relates to a device (10) comprising: • a source electrode (3) and a drain electrode (2) in contact with an active layer (15); A gate electrode (4) between the source (3) and drain (2) electrodes, having a drain side facing the drain electrode (2) and a source side facing the source electrode (3); ); A first field plate (FP1) disposed at least partially between the gate electrode (4) and the drain electrode (2) at a first distance from the active layer (15); The device (10) is remarkable in that the first field plate (FP1) comprises a plurality of first blocks (18) arranged side by side along a first distribution line (19) which follows the drain side of the grate (4).

Description

DEVICE WITH SEGMENTED FIELD PLATES FIELD OF THE INVENTION

The present invention relates to high voltage devices. In particular, it relates to a configuration of segmented field plates for a high-voltage device.

BACKGROUND OF THE INVENTION

Element III nitride semiconductors, also known as III-N semiconductor nitrides, have been known for some decades as excellent candidates for high power and high frequency applications. Indeed, the field effect transistors (FETs) based on heterojunctions made of materials composed of III-N semiconductor nitrides are able to withstand very high voltages and voltages. pass high current densities with low resistive losses.

In the blocking state of such a transistor 1, the potential on the terminal of the drain electrode 2 can be from a few hundred volts to a few thousand volts, while the terminals of the source electrode 3 and the gate 4 are grounded or at a very low potential with respect to each other: an important electric field then develops, in particular between the gate 4 and the drain 2, capable of inducing the breakdown of the gate oxide 5.

Field plates ("field plates" according to the English terminology) have been integrated in the stack of layers forming the transistor: their main function is to reshape the distribution of the electric field in the conduction channel of the transistor and to avoid excessive concentration of electric field at the edge of the gate electrode.

The benefit of the introduction of these field plates is in particular an increase in the voltage withstand of the device (breakdown voltage).

The field plates are usually formed of a conductive material, and extend above the gate to the drain, in a longitudinal direction, so as to fulfill their role of screening the electric field developing between the gate and the gate. drain. They can be electrically connected to source 3 (FPS for "field plate Source") and / or gate 4 (FPG for "field plate Gate") as shown in Figure 1.

A disadvantage of the presence of field plates above the gate 4 and / or above the active layer is the introduction of additional parasitic capacitances, in particular between the source 3 and the gate 4.

EP2538446 discloses a multiple field plate configuration for reducing the electric field peak in the device and thus improving the breakdown voltage.

OBJECT OF THE INVENTION

An object of the invention is to propose an alternative solution of field plates making it possible to reduce the electric field concentration at the gate in the off state of a device, while limiting the generation of parasitic capacitances. An object of the invention is in particular a high voltage device provided with at least one level of segmented field plate.

BRIEF DESCRIPTION OF THE INVENTION The invention relates to a device comprising: a source electrode and a drain electrode in contact with an active layer; A gate electrode between the source and drain electrodes, having a drain side facing the drain electrode and a source side facing the source electrode; A first field plate, disposed at least partially between the gate electrode and the drain electrode, at a first distance from the active layer;

The device is notable in that the first field plate comprises a plurality of first pads arranged side by side in a first distribution line which follows the drain side of the gate electrode.

The field plate according to the invention is segmented into a plurality of first blocks in a plane parallel to the active layer; these first blocks are arranged along a distribution line which follows the shape of the drain side of the gate electrode. This configuration makes it possible to remodel the distribution of the electric field, resulting from the potential difference between the drain electrode and the gate electrode, close to the drain side of the gate. The segmentation of the first field plate into a plurality of blocks also has the advantage of reducing the metal conductor surface in the stack and thus limiting the introduction of parasitic capacitances.

According to advantageous features of the device according to the invention, taken alone or in combination: • the first field plate comprises an element disposed along the first distribution line and in contact with the plurality of first blocks; Each first block is segmented into at least two first sub-blocks in a direction orthogonal to the first distribution line; • the device comprises a second field plate disposed at least partially between the gate electrode and the drain electrode at a second distance from the active layer; The second field plate comprises a plurality of second blocks arranged side by side along a second distribution line which follows the drain side of the gate electrode; Each second block is segmented into at least two second sub-blocks in a direction orthogonal to the second distribution line; all or part of the field plates are floating; • all or part of the field plates is electrically connected to the source; • all or part of the field plates is electrically connected to the grid; The device comprises a field effect transistor (FET); The device comprises a high electron mobility transistor (HEMT); The active layer comprises at least one material of the group of III-N semiconductor nitrides; • all or part of the pavers and / or sub-pavers is formed by conductive vias.

BRIEF DESCRIPTION OF THE DRAWINGS Other characteristics and advantages of the invention will emerge from the detailed description of the invention which will follow with reference to the appended figures in which:

Figure 1 shows a high voltage transistor of the state of the art; Figures 2, 3, 4, 5, 6 and 7 show top views (a) and section (b, c) of several variants of a device provided with a first segmented field plate according to the invention; Figures 8a, 8b and 8c show top views (a) and section (b, c) of a device provided with a first and a second segmented field plate according to the invention;

DETAILED DESCRIPTION OF THE INVENTION

The figures are diagrammatic representations of devices in section or in plan view in which the lateral or vertical dimensions may not be respected. In addition, to allow easier visualization of segmented field plate configurations according to the invention, a top view may in some cases represent elements in several vertical planes (along the z axis in the figures) different.

The configuration of field plates according to the invention can be implemented in various devices, in particular field effect transistors (FET) and / or high electron mobility transistors (HEMTs for "high electron mobility transistor") according to the English terminology. Saxon), based on wide band gap materials, adapted to withstand high voltages.

In particular, such devices can be developed on a structure comprising a stack of layers formed of III-N semiconductor nitrides, disposed on a support substrate, for example silicon, sapphire, silicon carbide or other support compatible with growth. epitaxial material III-N. A nucleation layer is usually deposited on the substrate to reduce the mismatch between the support substrate and the next layer, called the buffer layer 11, of III-N material (eg GaN). Finally, a barrier layer 12 also made of III-N material (for example AlGaN) is placed on the buffer layer. A two-dimensional electron gas layer (2DEG) 13 may be developed near the interface between the buffer layer 11 and the barrier layer 12 (heterojontion), to constitute the channel of conduction of the future device elaborated on the structure.

As illustrated in FIG. 2b, the device 10 according to the invention comprises an active layer 15 formed of semiconductor materials; in the exemplary structure III-N material above, the active layer 15 comprises in particular the heterojunction at which the 2DEG layer 13 constituting the conduction channel may develop.

The device 10 further comprises source 3 and drain 2 electrodes in electrical contact with the active layer 15 and in particular forming an ohmic contact with the heterojunction. The source 3 and drain 2 electrodes may be formed of different materials including, but not limited to, alloys of titanium, aluminum, tungsten, nickel, palladium, gold, etc. The spacing between the source electrode 3 and the drain electrode 2 defines the length of the conduction channel.

In the remainder of this description, the direction parallel to the length of the channel will be named longitudinal direction (along the axis y in the figures). The direction perpendicular to the longitudinal direction, in the plane (x, y) of the active layer 15, will be named transverse direction (along the x axis in the figures). Finally, the direction perpendicular to the plane of the active layer 15 will be called the vertical direction (along the z axis in the figures).

The device 10 also comprises a gate electrode 4, formed between the source electrode 3 and the drain electrode 2, for switching the device from a blocking state (off) to an on state (on), allowing the displacement of the electrons in the underlying part of the conduction channel (layer 2DEG 13). The gate electrode 4, insulated from the active layer 15 by a gate oxide 5, can itself also be composed of different materials including but not limited to, titanium, aluminum, tungsten, nickel, palladium, gold, silicides, etc. By its arrangement, the gate electrode 4 has a drain side oriented towards the drain electrode 2 and a source side oriented towards the source electrode 3.

A first insulating layer 16, 17, comprising a dielectric layer or a combination of a plurality of dielectric layers, is formed on the active layer 15. It extends over at least a portion of the surface between the gate electrode 4 and the drain electrode 2 and on a portion of the surface between the gate 4 and the source 3. The first insulating layer 16, 17 may also extend over the gate electrode 4. By way of example, it may be formed by a material selected from silicon oxide, silicon nitride, aluminum oxide and have a thickness between 0.01 micron and 1 micron.

A first field plate (called FP1 for "field plate" thereafter) is then formed on or in the first insulating layer 16, 17: it is thus at a first distance from the active layer 15, in the vertical direction ( z axis). The FP1 field plate may be electrically connected to the gate electrode 4 or to the source electrode 3. Alternatively, it may be floating.

The FPl field plate may be composed of a material chosen from aluminum, polysilicon, tungsten, copper or their alloys. Advantageously, it may be formed during the step of producing the gate electrode 4.

It is arranged at least partly between the gate electrode 4 and the drain electrode 2 in the longitudinal direction.

According to the invention, the first field plate FP1 comprises a plurality of blocks 18, arranged side by side in a plane (x, y) parallel to that of the active layer 15 (FIG. 2a). The pavers 18 are arranged along a distribution line 19 which follows the drain side of the gate electrode 4. The distribution line 19 may result in a fictitious line on which the pavers 18 are aligned by one of their sides. . In the longitudinal direction, the distribution line 19 is located at a distance dG-FPi from the drain side of the gate electrode 4. The case where the distribution line 19 is located somewhere in line with the gate 4 would result in a negative dG-FPi distance.

For clarity later, the pavers 18 will be named first blocks and the distribution line 19 will be named first distribution line.

The dimensions of the first blocks 18 and their spacing make it possible to modify the distribution of the electric field induced by the potential difference between gate 4 and drain 2 in the blocking state of device 10.

According to a first variant, illustrated in FIGS. 3a and 3b, the FPl field plate is connected to the source 3. Advantageously, it is then chosen not to have the plurality of first blocks 18 directly above the gate electrode. 4 to limit the introduction of grid / source parasitic capacitances. The first blocks 18 are arranged strictly between the gate electrode 4 and the drain electrode 2 in the longitudinal direction, that is to say that dG-Fpi is greater than or equal to 0. Preferably, the first line of distribution 19, on which the first blocks 18 are arranged, extends over the entire width of the gate electrode 4. The size of the first blocks 18 in the longitudinal direction may be between 0.1 and 5 microns. It is defined in particular as a function of the distance between the gate electrode 4 and the drain electrode 2. The dimension of a first pad 18 and the spacing between two adjacent first blocks in the transverse direction (x axis) can be respectively between 0.1 and 5 microns and between a few nanometers and 10 microns.

The transverse dimension and the spacing between two adjacent first pavers 18 are chosen, as a function of the potential on the drain electrode 2, so as to optimize the effect of reducing the electric field while minimizing the parasitic capacitances.

According to a second variant, the field plate FP1 is connected to the gate 4. It may be located at different distances from the active layer 15, either on the insulating layer 16, or in the insulating layer 17 (FIG. 2), or again on the insulating layer 17 (Figure 3). The first blocks 18 are advantageously arranged at a distance dG-FPi with respect to the drain side of the gate electrode in the longitudinal direction, strictly greater than 0: this separation between the gate electrode and the first FP1 field plate allows to reduce the CGD capacity. Preferably, the first distribution line 19, on which the first blocks 18 are arranged, extends over the entire width of the gate electrode 4. The dimensions of the first blocks 18 and their spacing can be chosen in the same ranges as in FIG. previously stated for the first variant.

According to a third variant, the first FP1 field plate is floating. In this configuration, it can take one of the shapes and dimensions described in the previous variants.

According to a fourth variant, illustrated in FIGS. 4a, 4b and 4c, the first field plate FP1 comprises an element 180 disposed along the first distribution line 19 and in contact with the plurality of first blocks 18 (FIG. 4a). Figures 4b and 4c respectively show the sectional views along the planes symbolized by the dashed lines (b) and (c) in Figure 4a. Advantageously, the element 180 of the field plate FP1 will be located between the drain side of the gate electrode 4 and the plurality of blocks 18. It allows a continuous shielding of the electric field along the drain side of the electrode. grid 4. The segmentation of the remainder of the surface (in the plane (x, y)) of the first field plate FP1 in the plurality of first blocks 18 is then advantageous for limiting the conductor surface and therefore parasitic capacitances. In FIG. 4, the first FP1 field plate is connected to the gate. Alternatively, FP1 provided with the element 180, can be connected to the source or be floating.

According to a fifth variant, an additional field plate 181 according to the state of the art, that is to say not segmented in the transverse direction, may be developed on the first insulating layer 16, 17, according to a distribution line which follows the drain side of the gate electrode 4, prior to the manufacture of FP1. FIG. 5 illustrates this case with, for example, an additional field plate 181, connected to the gate 4 and in continuity with it. The first FP1 field plate may then be formed according to one of the four previous variants. The additional field plate 181 and FP1 may be at the same first distance from the active layer 15, in the vertical direction or at different distances.

Optionally, and in any of the implementation variants mentioned above, each first block 18 of the first field plate FP1 may be segmented into at least two sub-blocks 18 ', 18' ', in the longitudinal direction ( orthogonal to the first distribution line 19). This configuration is illustrated in plan view in FIG. 6a and in sectional view in FIG. 6b. This segmentation makes it possible to divide the intensity of the electric field, always in order to avoid its concentration at the edge of the gate electrode, while limiting the metal surface of the field plates.

In the device according to the invention, a second field plate (called FP2 for "field plate" later) can also be formed: it is at a second distance from the active layer 15, in the vertical direction and is separated of the first FP1 field plate by an insulating layer. This insulating layer may be as in the example illustrated in FIG. 8, the layer 17, the first field plate FP1 being formed on the insulating layer 16 below. If FP1 is formed on the insulating layer 17, a second insulating layer may be formed over at least a portion of the first FP1 field plate and at least a portion of the first insulating layer between FP1 and the drain electrode. This second insulating layer may comprise a dielectric layer or a combination of a plurality of dielectric layers. For example, it may be formed by a dielectric material selected for example from silicon oxide, silicon nitride, and have a thickness between 0.1 and 10 microns.

The FP2 field plate may be electrically connected to the gate electrode or the source electrode. Alternatively, it can be floating.

The FP2 field plate is composed of a material identical or not to the material of the first FPl field plate, chosen from aluminum, polysilicon, tungsten, copper, nickel, palladium, gold or their alloys. .

It is arranged at least partly between the gate electrode 4 and the drain electrode 2 in the longitudinal direction (y-axis). Advantageously, to tend to form a gradual electric field between the gate electrode 4 and the drain electrode 2, the second field plate FP2 is disposed between the first field plate FP1 and the drain electrode 2, according to the longitudinal direction (FIG. 8), ie at a distance dG-FP2 from the drain side of the gate electrode 4.

According to the invention, the second field plate FP2 may also comprise a plurality of blocks 28, arranged side by side in a plane (x, y) parallel to that of the active layer 15. The blocks are arranged along a distribution line 29 following the drain side of the gate electrode 4. For clarity later, the blocks 28 of the second FP2 field plate will be named second blocks and the associated distribution line 29 will be named second distribution line.

Advantageously, but without limitation, in the longitudinal direction, the second blocks 28 will be placed vis-à-vis the spacing zones between the first blocks 18, as shown in Figure 8a.

The five variants described for the first FP1 field plate can be applied to the second FP2 field plate. The described ranges of paver dimensions and spacing between pavers are also applicable.

The segmentation of the second pavers 29 in sub-pavers can also be implemented.

Note that one or more additional field plate (s) conventionally used in the prior art, may (have) be formed before or after FP1 or FP2, at a distance less than, equal to or greater than the first distance between FP1 and the active layer 15 in the vertical direction.

According to an advantageous embodiment, the first 18 and / or second 28 blocks are formed by conductive vias (FIG. 7). The vias, very commonly used in microelectronic technologies, are formed by trenches, the walls of which comprise a layer of electrical insulating material, which are filled with an electrically conductive material (for example tungsten, aluminum, copper, titanium ...); they are conventionally developed during a process for manufacturing microelectronic components, for connecting metal levels to each other. In this embodiment of the first 18 and / or second 28 blocks, the conductive vias are not necessarily connected to an underlying metal. The use of the steps of developing conductive vias for the realization of pavers 18,28 allows optimization of the manufacturing steps: only a modification of the mask (s) of the target vias levels is necessary, without adding steps specific manufacturing for field plates.

Of course, the invention is not limited to two levels of field plates (FP1 and FP2) nor to the described field plate geometries; other levels of field plates may be added according to the developed device and arranged according to different adapted configurations.

The distance between the field plate closest to the drain electrode 2 should preferably be kept at least greater than 1 micron, depending on the use voltage of the component, to avoid the breakdown of the insulating layer between said plate field and the drain electrode 2.

Example 1

According to a first example, the device consists of a HEMT transistor produced on a GaN-based structure, comprising a hetero junction capable of developing a two-dimensional gas which will form the conduction channel. The HEMT transistor has a lateral configuration, with source 3 and drain 2 electrodes in the form of interdigitated fingers, 5 microns apart. The gate electrode 4 is disposed between the source 3 and drain 2 electrodes and has a substantially rectangular shape with a drain side facing the drain electrode and a source side oriented towards the source electrode. Its dimension in the longitudinal direction is about 1 micron. In the "off" state of the transistor, the drain electrode 2 has a potential of 600 volts, while the source potential is 0 volts and the gate potential is -5 volts.

The first FPl field plate is disposed on a first insulating layer 16 formed of 0.2 micron thick SiN. The field plate FP1 has a plurality of first blocks 18, arranged at a distance dG-FPi equal to 0.1 micron. The transverse and longitudinal dimensions (in the plane (x, y)) of each first block 18 are respectively 1 micron and 1 micron. The spacing between two adjacent pavers 18 is 1 micron.

The second field plate FP2 is formed in the insulating layer 17: it is formed of 0.2 micron thick SiO 2 and covers the gate electrode 4 and FP1. The field plate FP2 has a plurality of second blocks 28 arranged at a distance dG-FP2 equal to 2.2 micron. These second blocks 28 are formed by conductive vias tungsten, circular section of 1 micron. The spacing between two adjacent blocks 28 is 1 micron. In the longitudinal direction, the second blocks 28 are placed opposite the spacing zones between the first blocks 18.

This configuration advantageously lowers the intensity of the electric field generated by the potential difference between drain 2 and gate 4. It also makes it possible to limit parasitic capacitances due to the reduction of the metal surfaces of the field plates.

Example 2

According to a second example, the device consists of a HEMT transistor produced on a GaN-based structure, comprising a hetero junction capable of developing a two-dimensional gas which will form the conduction channel. The lateral HEMT transistor has a circular topology with a circular central drain electrode, a gate electrode forming a ring around the drain electrode, and a source electrode disposed around the gate electrode. The drain electrode is distant from the source electrode of 5 microns.

In the case of a circular topology, the longitudinal direction mentioned above becomes the radial direction and the transverse direction becomes the tangential direction.

The first FP1 field plate is formed in the first insulating layer by 1 micron conductive vias of circular section. In the plane (x, y), the field plate FP1 has a plurality of first blocks, arranged at a distance dG-FPi equal to 0.1 micron, along a distribution line which follows the drain side of the ring formed by the gate electrode. The spacing between two adjacent pavers is 1 micron. Alternatively, the tiles may have a square shape, rectangle or a form of ring sector, in the plane (x, y).

The second FP2 field plate is formed in a second insulating layer formed of 0.2 micron thick SiO 2. The FP2 field plate has a plurality of second blocks arranged at a distance dG-FP2 equal to 2.2 micron, along a distribution line which follows the drain side of the ring formed by the gate electrode. These second blocks are formed by conductive vias of 1 micron circular section. The spacing between two adjacent pavers is 1 micron. In the radial direction, the second blocks are placed next to the spacing zones between the first blocks.

One or more other FPn field plates according to the invention may be added if necessary to manage the electric field between gate and drain.

This configuration of field plates according to the invention advantageously lowers the intensity of the electric field generated by the potential difference between drain and gate. It also makes it possible to limit the parasitic capacitances due to the reduction of the metal surfaces of the field plates.

Of course, the invention is not limited to the embodiments described and variants can be made without departing from the scope of the invention as defined by the claims.

The device according to the invention may also consist of or comprise other types of high voltage side components such as a silicon MOS transistor, LDMOS, a GaAs HEMT transistor, GaN, etc.

Claims (13)

Apparatus (10) comprising: • a source electrode (3) and a drain electrode (2) in contact with an active layer (15); A gate electrode (4) between the source (3) and drain (2) electrodes, having a drain side facing the drain electrode (2) and a source side facing the source electrode (3); ); A first field plate (FP1) disposed at least partially between the gate electrode (4) and the drain electrode (2) at a first distance from the active layer (15); The device (10) being characterized in that the first field plate (FP1) comprises a plurality of first blocks (18) arranged side by side along a first distribution line (19) which follows the drain side of the grate (4). 2. Device (10) according to the preceding claim, wherein the first field plate (FP1) comprises an element (180) disposed along the first distribution line (19) and in contact with the plurality of first blocks (18). 3. Device (10) according to one of the preceding claims, wherein each first block (18) is segmented into at least two first sub-blocks (18 ', 18' ') in a direction orthogonal to the first distribution line (19). 4. Device (10) according to one of the preceding claims, comprising a second field plate (FP2), arranged at least partly between the gate electrode (4) and the drain electrode (2), at a distance of second distance from the active layer (15). 5. Device (10) according to the preceding claim, wherein the second field plate (FP2) comprises a plurality of second blocks (28) arranged side by side along a second distribution line (29) which follows the drain side of the gate electrode (4). 6. Device (10) according to one of the two preceding claims, wherein each second block (28) is segmented into at least two second sub-blocks in a direction orthogonal to the second distribution line (29). 7. Device (10) according to one of the preceding claims, wherein all or part of the field plates (FP1, FP2) is floating. 8. Device (10) according to one of claims 1 to 6, wherein all or part of the field plates (FP1, FP2) is electrically connected to the source (3). 9. Device (10) according to one of claims 1 to 6, wherein all or part of the field plates (FP1, FP2) is electrically connected to the gate (4). 10. Device (10) according to one of the preceding claims, comprises a field effect transistor (FET). 11. Device (10) according to one of the preceding claims, comprises a high electron mobility transistor (HEMT). 12. Device (10) according to one of the preceding claims, wherein the active layer (15) comprises at least one material of the group of III-N semiconductor nitrides. 13. Device (10) according to one of the preceding claims, wherein all or part of the pavers (18,28) and / or sub-pavers is formed by conductive vias.