FR3042051B1 - IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR - Google Patents

IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR

Info

Publication number
FR3042051B1
FR3042051B1 FR1559369A FR1559369A FR3042051B1 FR 3042051 B1 FR3042051 B1 FR 3042051B1 FR 1559369 A FR1559369 A FR 1559369A FR 1559369 A FR1559369 A FR 1559369A FR 3042051 B1 FR3042051 B1 FR 3042051B1
Authority
FR
France
Prior art keywords
mono
implementing
wire
core processor
atomic operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1559369A
Other languages
French (fr)
Other versions
FR3042051A1 (en
Inventor
Fabrice Devaux
David Furodet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Upmem SAS
Original Assignee
Upmem SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Upmem SAS filed Critical Upmem SAS
Priority to FR1559369A priority Critical patent/FR3042051B1/en
Priority to PCT/FR2016/052462 priority patent/WO2017055742A1/en
Publication of FR3042051A1 publication Critical patent/FR3042051A1/en
Application granted granted Critical
Publication of FR3042051B1 publication Critical patent/FR3042051B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
FR1559369A 2015-10-02 2015-10-02 IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR Active FR3042051B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1559369A FR3042051B1 (en) 2015-10-02 2015-10-02 IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR
PCT/FR2016/052462 WO2017055742A1 (en) 2015-10-02 2016-09-28 Implementation of an atomic operation on a multi-threaded single-core processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1559369A FR3042051B1 (en) 2015-10-02 2015-10-02 IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR

Publications (2)

Publication Number Publication Date
FR3042051A1 FR3042051A1 (en) 2017-04-07
FR3042051B1 true FR3042051B1 (en) 2017-11-24

Family

ID=55361601

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1559369A Active FR3042051B1 (en) 2015-10-02 2015-10-02 IMPLEMENTING AN ATOMIC OPERATION ON A MULTI-WIRE MONO-CORE PROCESSOR

Country Status (2)

Country Link
FR (1) FR3042051B1 (en)
WO (1) WO2017055742A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115269015B (en) * 2022-09-26 2022-12-02 沐曦集成电路(南京)有限公司 Shared variable processing system based on Atomic instruction

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7680989B2 (en) * 2005-08-17 2010-03-16 Sun Microsystems, Inc. Instruction set architecture employing conditional multistore synchronization
US9678897B2 (en) * 2012-12-27 2017-06-13 Nvidia Corporation Approach for context switching of lock-bit protected memory

Also Published As

Publication number Publication date
FR3042051A1 (en) 2017-04-07
WO2017055742A1 (en) 2017-04-06

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