FR3035243B1 - Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique - Google Patents

Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique Download PDF

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Publication number
FR3035243B1
FR3035243B1 FR1553478A FR1553478A FR3035243B1 FR 3035243 B1 FR3035243 B1 FR 3035243B1 FR 1553478 A FR1553478 A FR 1553478A FR 1553478 A FR1553478 A FR 1553478A FR 3035243 B1 FR3035243 B1 FR 3035243B1
Authority
FR
France
Prior art keywords
calculation
instructions
calibration data
placing
task
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1553478A
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English (en)
Other versions
FR3035243A1 (fr
Inventor
Alexandre AMINOT
Yves Lhuillier
Andrea CASTAGNETTI
Alain CHATEIGNER
Henri-Pierre CHARLES
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1553478A priority Critical patent/FR3035243B1/fr
Priority to US15/567,067 priority patent/US20180095751A1/en
Priority to EP16711185.5A priority patent/EP3286647A1/fr
Priority to PCT/EP2016/055401 priority patent/WO2016173766A1/fr
Publication of FR3035243A1 publication Critical patent/FR3035243A1/fr
Application granted granted Critical
Publication of FR3035243B1 publication Critical patent/FR3035243B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30083—Power or thermal control instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Debugging And Monitoring (AREA)

Abstract

La présente invention concerne un procédé pour la gestion d'une tâche de calcul sur un processeur multi-coeurs fonctionnellement asymétrique, au moins un cœur dudit processeur étant associé à une ou plusieurs extensions matérielles, le procédé comprenant les étapes consistant à recevoir une tâche de calcul associée à des instructions exécutables par une extension matérielle; recevoir des données de calibration associées à l'extension matérielle; et déterminer un coût d'opportunité d'exécution de la tâche de calcul en fonction des données de calibration. Des développements décrivent la détermination des données de calibration notamment par comptage ou par calcul (en ligne et/ou hors ligne) des classes des instructions exécutées, l'exécution d'un ensemble prédéfini d'instructions représentatif de l'espace d'exécution de l'extension, la prise en compte d'aspects énergétiques et de température, la traduction ou l'émulation d'instructions ou le placement de tâches de calcul sur les différents coeurs. Des aspects de système et de logiciel sont décrits.
FR1553478A 2015-04-20 2015-04-20 Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique Expired - Fee Related FR3035243B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1553478A FR3035243B1 (fr) 2015-04-20 2015-04-20 Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique
US15/567,067 US20180095751A1 (en) 2015-04-20 2016-03-14 Placement of a calculation task on a functionally asymmetric processor
EP16711185.5A EP3286647A1 (fr) 2015-04-20 2016-03-14 Placement d'une tâche de calcul sur un processeur fonctionnellement asymetrique
PCT/EP2016/055401 WO2016173766A1 (fr) 2015-04-20 2016-03-14 Placement d'une tâche de calcul sur un processeur fonctionnellement asymetrique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1553478 2015-04-20
FR1553478A FR3035243B1 (fr) 2015-04-20 2015-04-20 Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique

Publications (2)

Publication Number Publication Date
FR3035243A1 FR3035243A1 (fr) 2016-10-21
FR3035243B1 true FR3035243B1 (fr) 2018-06-29

Family

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FR1553478A Expired - Fee Related FR3035243B1 (fr) 2015-04-20 2015-04-20 Placement d'une tache de calcul sur un processeur fonctionnellement asymetrique

Country Status (4)

Country Link
US (1) US20180095751A1 (fr)
EP (1) EP3286647A1 (fr)
FR (1) FR3035243B1 (fr)
WO (1) WO2016173766A1 (fr)

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KR102285481B1 (ko) * 2015-04-09 2021-08-02 에스케이하이닉스 주식회사 NoC 반도체 장치의 태스크 매핑 방법
US10700968B2 (en) * 2016-10-19 2020-06-30 Rex Computing, Inc. Optimized function assignment in a multi-core processor
US10355975B2 (en) 2016-10-19 2019-07-16 Rex Computing, Inc. Latency guaranteed network on chip
JP2018092311A (ja) * 2016-12-01 2018-06-14 キヤノン株式会社 情報処理装置、その制御方法、及びプログラム
US11934945B2 (en) 2017-02-23 2024-03-19 Cerebras Systems Inc. Accelerated deep learning
US11488004B2 (en) 2017-04-17 2022-11-01 Cerebras Systems Inc. Neuron smearing for accelerated deep learning
US11232347B2 (en) 2017-04-17 2022-01-25 Cerebras Systems Inc. Fabric vectors for deep learning acceleration
US10795836B2 (en) * 2017-04-17 2020-10-06 Microsoft Technology Licensing, Llc Data processing performance enhancement for neural networks using a virtualized data iterator
WO2018193352A1 (fr) 2017-04-17 2018-10-25 Cerebras Systems Inc. Tâches déclenchées par un flux de données pour apprentissage profond accéléré
WO2020044152A1 (fr) 2018-08-28 2020-03-05 Cerebras Systems Inc. Textile informatique mis à l'échelle pour apprentissage profond accéléré
WO2020044208A1 (fr) 2018-08-29 2020-03-05 Cerebras Systems Inc. Améliorations apportées à une architecture de jeu d'instructions (isa) pour un apprentissage profond accéléré
WO2020044238A1 (fr) 2018-08-29 2020-03-05 Cerebras Systems Inc. Redondance d'élément de processeur pour apprentissage profond accéléré
US11188617B2 (en) * 2019-01-10 2021-11-30 Nokia Technologies Oy Method and network node for internet-of-things (IoT) feature selection for storage and computation
US12008398B2 (en) * 2019-12-28 2024-06-11 Intel Corporation Performance monitoring in heterogeneous systems
US11775298B2 (en) * 2020-04-24 2023-10-03 Intel Corporation Frequency scaling for per-core accelerator assignments
US11989591B2 (en) * 2020-09-30 2024-05-21 Advanced Micro Devices, Inc. Dynamically configurable overprovisioned microprocessor

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JP4784827B2 (ja) * 2006-06-06 2011-10-05 学校法人早稲田大学 ヘテロジニアスマルチプロセッサ向けグローバルコンパイラ
US8782645B2 (en) * 2011-05-11 2014-07-15 Advanced Micro Devices, Inc. Automatic load balancing for heterogeneous cores
US9720730B2 (en) 2011-12-30 2017-08-01 Intel Corporation Providing an asymmetric multicore processor system transparently to an operating system
KR20130115574A (ko) * 2012-04-12 2013-10-22 삼성전자주식회사 단말기에서 태스크 스케줄링을 수행하는 방법 및 장치
US20150355700A1 (en) * 2014-06-10 2015-12-10 Qualcomm Incorporated Systems and methods of managing processor device power consumption

Also Published As

Publication number Publication date
WO2016173766A1 (fr) 2016-11-03
US20180095751A1 (en) 2018-04-05
EP3286647A1 (fr) 2018-02-28
FR3035243A1 (fr) 2016-10-21

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