FR3033664A1 - ADJUSTABLE THRESHOLD VOLTAGE TRANSISTOR - Google Patents

Abstract

A high electron mobility field effect transistor (1) comprises: first and second semiconductor layers (12, 13) superimposed to form an electron gas layer (14) at their interface; a control gate (2) formed on the second semiconductor layer (13); Wherein the control gate (2) comprises: a first gate oxide layer (22); nanocrystals (23) of conductive or semiconductor material, the nanocrystals having an electrostatic charge, said nanocrystals being electrically isolated from each other by the first gate oxide layer; a gate metal (21) formed on the first gate oxide layer (22).

Description

The invention relates to high-mobility electronic transistors based on the presence of heterojunctions, and in particular the manufacture of such normally-blocked type transistors. Numerous electronic applications now require performance improvements, especially in on-board electronics for the automotive and land transport industries, in aeronautics, in medical systems or in home automation solutions, for example. These applications require for the most part high power switches operating in frequency ranges frequently greater than the megahertz. Historically, power switches have long relied on field effect transistors based on a semiconductor channel, most often silicon. For lower frequencies, junction transistors are preferred because they support higher current densities. However, because of the relatively limited breakdown voltage of each of these transistors, the power applications require the use of a large number of series transistors, or longer transistors, resulting in passing resistance. higher. The losses through these series transistors are considerable, both in steady state and in commutation. An alternative for power switches, especially at high frequencies, is the use of high electron mobility field effect transistors, also referred to as heterostructure field effect transistors. Such a transistor includes the superposition of two semiconductor layers having different forbidden bands which form a quantum well at their interface. Electrons are confined in this quantum well to form a two-dimensional gas of electrons. For reasons of resistance to high voltage and temperature, these transistors are chosen so as to have a wide band of forbidden energy. For certain applications, in particular safety applications for isolating a circuit in the event of a malfunction of a control system, normally-blocked type HEMT transistors are used, that is to say that their threshold voltage of switching is positive, so that the transistor remains blocked in the absence of a control signal. Because of the inherently conductive nature of the electron gas layer formed between a source and a drain, it is technologically easier to provide a normally-passed heterojunction transistor. However, several manufacturing processes have been developed to form normally blocked type heterojunction transistors. It is known to produce Schottky type control gates for heterojunction transistors of normally blocked type. However, such transistors are unsuitable for power electronics due to current leakage levels between gate and drain and due to the sensitivity of the current / voltage curve to temperature. Various manufacturing methods have also been developed for producing MIS type grids for heterojunction transistors of normally blocked type.

According to a first approach, a binary layer of type III nitride and a ternary layer of type III nitride are superimposed to form a layer of electron gas at the interface between these nitrides. A recess is made by etching in the ternary nitride layer in order to locally reduce the thickness of this ternary layer. When the local thickness of the ternary layer of nitride is sufficiently low, for example from 2 to 3 nm for AlGaN, the electron gas disappears at the recess. Then, the grid is formed at the recess. The process of etching the recess is still insufficiently controlled to ensure a satisfactory thickness of the ternary nitride layer in the recess. According to an alternative, the etching is carried out up to the nitride binary layer, with the disadvantage of locally having a MOSFET-type operation and thus a raised on-state resistance. In addition, the surface state obtained during the etching of the recess involves trapping a large amount of charges during the subsequent formation of a gate insulator, which disrupts the operation of the transistor. According to a second approach, a binary layer of type III nitride and a ternary layer of type III nitride are superimposed to form a layer of electron gas at the interface between these nitrides. P type doping of the upper part of the ternary nitride layer is carried out, followed by etching of the doped part to preserve a doped element at the level of the grid to be formed. The surface condition obtained during this engraving is bad. In addition, this method is incompatible with grids of the MIS type, which induces leakage between the grid and the drain of an excessive level.

According to a third approach, a binary type III nitride binary layer and a ternary type III nitride layer are superimposed to form a layer of electron gas at the interface between these nitrides. P-type doping is carried out by implantation in the binary layer or in the ternary layer to the electron gas layer, at the level of the gate to be formed. However, the implanted dopants require activation that is difficult to implement, in particular by the necessity of heating at a temperature greater than 900 °, incompatible with CMOS technology. Such a method allows the formation of a MIS type gate but is not compatible with threshold voltage matching parameters. Consequently, the threshold voltage of the transistors obtained has large dispersions for different batches of transistors. According to a fourth approach, a binary layer of type III nitride and a ternary layer of type III nitride are superimposed to form a layer of electron gas at the interface between these nitrides. A gate insulator is formed in which electrostatic charges are trapped, and the gate metal is formed on this insulator. The trapped electrostatic charges make it possible to adjust more precisely the value of the threshold voltage of the HEMT transistor. The gate insulator is usually formed by superimposing a bottom layer of charged insulator surmounted by a top layer of unfilled insulator. The lower layer of insulation is for example charged as soon as it is deposited or by an implantation step. Such a method results in practice in trapping charges at the interface between the lower layer and the upper layer, which induces high dispersions of the threshold voltages of the transistors formed.

The invention aims to solve one or more of these disadvantages. The invention thus relates to a high electron mobility field effect transistor, comprising: first and second semiconductor layers superimposed to form a layer of electron gas at their interface; A control gate formed on the second semiconductor layer; Wherein the control gate comprises: a first gate oxide layer; nanocrystals of conducting or semiconductor material, the nanocrystals having an electrostatic charge, said nanocrystals being electrically isolated from each other by the first gate oxide layer, a gate metal formed on the first layer of gate oxide. According to one variant, the relative dielectric permeability of the first gate oxide layer is at least 5. According to another variant, said first gate oxide layer essentially contains Al 2 O 3.

According to another variant, the transistor comprises a second gate oxide layer disposed between the nanocrystals and the second semiconductor layer. According to yet another variant, said first and second gate oxide layers have the same chemical composition. Alternatively, said first gate oxide layer has a thickness greater than the second gate oxide layer. According to another variant, said first gate oxide layer has a thickness of between 6 and 20 nm and wherein said second gate oxide layer has a thickness of between 1 and 10 nm. According to one variant, said nanocrystals are positioned at an interface between the second semiconductor layer and said first gate oxide layer.

The invention further relates to a method for adjusting the threshold voltage of a high electron mobility field effect transistor, comprising the steps of: providing a high electron mobility field effect transistor, comprising: first and second semiconductor layers superimposed to form an electron gas layer at their interface; a control gate formed on the second semiconductor layer and having; a first layer of gate oxide; Nanocrystals of conductive or semiconductor material, said nanocrystals being electrically isolated from each other by the first gate oxide layer; a gate metal formed on the gate oxide layer; -Application of an electric field on the nanocrystals and on the interface 30 between the first and second semiconductor layers, so as to generate a tunnel current between said interface and said nanocrystals. Alternatively, said application of the electric field includes applying a potential on the gate metal greater than the potential on a conduction electrode of said high mobility electronic field effect transistor. According to another variant, the potential difference between the gate metal and said conduction electrode is at least equal to 5V and at most equal to 15V.

According to another variant, said nanocrystals apply an electrostatic field on the interface between said first and second semiconductor layers at the end of said application of said electric field, so that said transistor is then blocked in the absence of bias applied. on said gate metal. Other features and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limiting, with reference to the appended drawings, in which: FIGS. 1 and 2 are views in cutting two variants of HEMT transistors that can be implemented in the context of the invention; FIGS. 3 to 7 are sectional views of a transistor according to FIG. 1 during different stages of an example of a manufacturing method; FIG. 1 is a schematic cross-sectional view of a first example of HEMT type transistor 1 (also referred to as a high electron mobility field effect transistor) for carrying out the invention. . The transistor 1 comprises a substrate 11, optionally a buffer layer 20 not illustrated and arranged on the substrate 11, a semiconductor layer 12 (for example of III-V type, for example element III nitride, typically GaN), a semiconductor layer 13 made of another material (for example of III-V type, for example of element III nitride, typically AlGaN) and a layer of electron gas 14 intrinsically formed in a manner known per se to interface between the layers 12 and 13. The substrate 11 may be an insulator or semiconductor intrinsic or doped silicon type. The substrate 11 may, for example, be of silicon type with a mesh orientation (111). The substrate 11 may also be silicon carbide, or sapphire. The substrate 11 may have a thickness of the order of 650 μm, typically between 500 μm and 2 mm. The buffer layer deposited on the substrate 11 serves as an intermediate between this substrate and the semiconductor layer 12, to allow mesh matching between the substrate 11 and the semiconductor layer 12. The buffer layer may typically be aluminum nitride .

The semiconductor layer 12 may typically have a thickness between 100 nm and 511m. The semiconductor layer 12 may be formed in a known manner by either epitaxy on the buffer layer. The semiconductor layer 12 is typically a binary element III nitride alloy, for example GaN.

The semiconductor layer 13, typically called a barrier layer, can typically have a thickness of between 5 nm and 40 nm, for example 25 nm. The semiconductor layer 13 may be formed in known manner by epitaxy on the semiconductor layer 12. The semiconductor layer 13 is typically a ternary alloy of element III nitride, for example AlGaN or binary alloy of Element III nitride, for example AlN. Transistor 1 comprises in a manner known per se conduction electrodes 16 and 17 disposed on the semiconductor layer 13. One of these electrodes will be designated as the source, the other electrode will be designated as the drain of transistor 1. A control gate 2 is positioned on the semiconductor layer 13 between the conduction electrodes 16 and 17. The control gate 2 comprises a gate oxide disposed on the semiconductor layer 13. The gate oxide is electrically insulating. The gate oxide comprises a lower layer 24 and an upper layer 22. Nanocrystals 23 are positioned at the interface between the lower layer 24 and the upper layer 22. A gate metal 21 is disposed on the upper layer 22.

Nanocrystals 23 are formed of electrically conductive material or semiconductor material. Nanocrystals 23 are electrically isolated from each other by the upper layer 22. The nanocrystals 23 have an electrostatic charge so that a zone 15 is formed at the interface between the layers 12 and 13 and vertically above the grid 2, 25 zone in which the electron gas is removed in the absence of polarization of the gate 21. The nanocrystals 23 and their electrostatic charges thus make it possible to form a HEMT transistor 1 of normally blocked type. Because the nanocrystals 23 are electrically insulated from each other, their electrostatic charges are more easily retained and the leakage of these electrostatic charges through the edges of the grid 2 are greatly reduced. This structure goes against the reflex of the skilled person, to achieve a continuous element to obtain a homogeneous electrostatic charge. The electrostatic charges of the nanocrystals 23 are obtained by the application of an electric field at the interface between the semi-conducting layers 12 and 13 under the gate 2, so as to pass the electrons of the electron gas layer. 14 to the nanocrystals 23 by tunnel effect. Such an electric field is for example generated by applying a potential difference between the gate metal 21 and one of the conduction electrodes 16 or 17, as will be detailed later. When the potential on the grid metal 21 is greater than the potential on one of the conduction electrodes, the electrons are attracted to the nanocrystals 23. Advantageously, the upper layer 22 and / or the lower layer 24 is of the high-voltage type. K, that is to say with high dielectric permeability. An insulating layer with a high dielectric permeability will subsequently designate a material whose relative dielectric permeability is at least equal to 5. Advantageously, this relative dielectric permeability will be at least equal to 6, or even at least equal to 7. The upper layer 22 may for example (but not limited to) be carried out in Al 2 O 3 HfO 2, Ta 2 O 5, ZrO 2, TiO 2 or in a mixture of these oxides, for example HfSiO, HfZrO, Nanolaminates HfO 2 / Al 2 O 3. The layer 22 will preferably be made of Al 2 O 3 produced by atomic layer deposition in chemical phase (ALD).

The use of an upper layer 22 and / or a lower layer 24 of the High-K type makes it possible to obtain a high electrostatic charge of the nanocrystals 23 (and therefore a significant threshold voltage variation for the transistor 1). even for a reduced programming voltage. Advantageously, the upper layer 22 and the lower layer 24 have the same chemical composition. Thus, the electrostatic charges trapped at the interface between the layers 22 and 24 are limited, which limits the dispersions for the threshold voltage of the transistor 1. The semiconductor nanocrystals 23 are, for example, silicon nanocrystals. The silicon nanocrystals may undergo annealing and / or post-treatment steps (eg treatment under nitrogen or carbon in an oven leading to the formation of SiN, SiC). The conducting nanocrystals 23 are, for example, metallic nanocrystals belonging to the Ni and Co columns in the periodic table of the elements advantageously Ni, Pd, Pt. The nanocrystals can also be formed in W, Ti, Ta. They can also be formed by alloying a transition metal element with silicon (silicide), nitrogen (nitride) or carbon (carbide) either directly during the deposition or by post-treatment in a furnace. annealed, for example WSi2, WN, TiN, TaN, TaC. Finally, the nanocrystals can also be in pure form of aluminum or of aluminum alloys (nitride, silicide or carbide), for example Al agglomerates, or WAI, WAIN. In general, the nanocrystals are advantageously spaced from each other by distances of between 1 and 2 nm.

The presence of the electron gas 14 at the interface between the semiconductor layers 12 and 13 makes it possible to have electrons in the vicinity of the nanocrystals 23 to charge these nanocrystals 23 by tunnel effect. The threshold voltage of the transistor 1 will be adjusted as a function of the electrostatic charge of the nanocrystals 23 by these electrons, at the origin of an electrostatic field pushing the electrons at the interface between the layers 12 and 13 under the gate 2. the lack of polarization of this grid. The threshold voltage of transistor 1 will thus be adapted as a function of the amplitude of the programming voltage and the duration of application of this programming voltage.

The sizing of the lower layer 24 and the upper layer 22 is determined to allow both an electron migration through the layers 13 and 24 by tunneling effect, and the absence of breakdown of the layers 13, 24 or 22 when applying a programming voltage. An equivalent toxic oxide or EOT thickness (corresponding to SiO 2) from the actual thickness tmat of an insulator is calculated by the following formula: EOT - (3.9 X tmat K) With K relative dielectric constant of the considered insulator, considering that the SiO 2 has a relative dielectric constant of 3.9. The electric field used to trap electrons in the nanocrystals 23 is between 1 and 10 MV / cm for SiO 2.

With layers 22 and 24 of A1203 and AlGaN layer 13: it is assumed that the actual thickness of the AlGaN layer 13 is 10 nm (EOT 4.59 nm with AlGaN having a relative dielectric permittivity of 8 , 5). Since the tunneling effect field across the layer 13 is 2.5 MV / cm, the voltage necessary to trigger a tunneling effect through the layer 13 alone is then 2.5 V; for example, it is desired to use a thickness EOT of mm of the layer 24 superimposed on the thickness of 10 nm of the AlGaN layer 13, with a thickness EOT of 10 nm for the layer 22; the electrical breakdown field of A1203 is approximated to 5 MV / cm and the electrical breakdown field of AlGaN is approximated to 5 MV / cm; for example, a layer 24 with a real thickness of 2 nm (for an EOT thickness of 0.74 nm, with K = 10.6) is used. Since the tunneling effect field across layer 24 is 2.5 MV / cm, the voltage required to trigger a tunneling effect across layer 24 alone is 2.5 V; for example, a layer 22 with an actual thickness of 8 nm (for an EOT thickness of 2.94 nm) is used. Since the tunneling effect field across the layer 22 is 2.5 MV / cm, the voltage required to trigger a tunneling effect across the layer 22 alone is 2 V; a programming voltage of 5 V is therefore sufficient to generate the loading tunnel effect of the nanocrystals 23. A programming voltage of 10V makes it possible not to induce breakdown of the layers 22, 24 and 13. With a layer of AlGaN 13 with a thickness of 20 nm (EOT of 9.18 nm), with layers 22 and 24 identical to those described above, a programming voltage of 7.5 proves to be sufficient to manage the nanocrystals loading tunnel effect 23. A programming voltage of 12.5V makes it possible not to induce breakdown of the layers 22, 24 and 13. In general, a layer 13 made of AlGaN will usually have a thickness of between 10 and 20. nm.

The lower layer 24 will advantageously have a real thickness of between 1 and 10 nm. This thickness may for example be 2 nm. The upper layer 22 will advantageously have a real thickness of between 6 and 20 nm. This thickness may for example be 825 nm, or 13 nm. The upper layer will have a thickness advantageously greater than that of the lower layer 24. In the absence of electrostatic charges in the nanocrystals 23, the transistor 1 behaves like a transistor of normal type. By applying an appropriate electrostatic charge in the nanocrystals 23, the transistor 1 is converted into a normally blocked type transistor. Thus, transistors in the same integrated circuit can selectively be of the normally conducting or normally blocked type, as a function of respective programming steps inducing different electrostatic charges in their nanocrystals 23 of different HEMT transistors. Positive threshold voltages of a transistor 1 will be obtained by charging the electron nanocrystals 23 by tunnel effect. It is also conceivable to obtain positive threshold voltages of a transistor 1 by applying a voltage on the control gate that is lower than that of one of its conduction electrodes, so that the programming voltage drives out the electrons. nanocrystals 23 by tunneling effect through the semiconductor layer 13 in particular. Re-programming can be performed during the life cycle of the integrated circuit, for example to modify or balance the threshold voltage of some transistors. The gate 2 of such a transistor 1 can be modeled as follows. The grid 2 can notably be modeled by two capacitors C1 and C2 in series, the capacitor C2 being formed by the upper insulating layer 22 between the gate metal 21 and the nanocrystals 23, and the capacitor C1 being formed by the layer lower insulation 24 between the nanocrystals 23 and the interface between the semiconductor layers 12 and 13. The Vfg will be designated the potential of the nanocrystals 23 and Qfg the charge of the nanocrystals 23. It is assumed that the capacitor C1 has an electrode connected to the ground while the capacitor C2 has an electrode connected to the gate potential Vg. The tunnel current will be designated by: -11in through the insulating layer 24 towards the nanocrystals 23; -11out the tunnel current through the insulating layer 24 from the nanocrystals 23; -I2in the tunnel current through the insulating layer 22 to the nanocrystals 23; -I2out the tunnel current through the insulating layer 22 from the nanocrystals 23; The following relations are then applicable: C2 Qfg Vfg - * Vg + C1 + C2 C1 + C2 dQfg = (Ili n + Ilout) - (12in + I2out) dt The currents 11in, 11 out, I2in and I2out are for example calculated with an approximation WKB (for Wentzel Kramers Brilloin). FIG. 8 illustrates a simulation of threshold voltage variation of a HEMT transistor as a function of a programming duration, for different programming voltages Vg, assuming a lower layer of a thickness of 5 nm in SiO 2 and an upper layer 22 with a thickness of 10 nm in SiO 2. FIG. 9 illustrates a simulation of a threshold voltage variation of a HEMT transistor as a function of a programming duration, for different programming voltages Vg, assuming a lower layer 24 with a real thickness of 2 nm in A1203 and an upper layer 22 with a real thickness of 8 nm in A1203. It can be seen that the amplitude of the programming voltages and the duration of their application are much smaller in this case to obtain a given threshold voltage variation.

Fig. 2 is a schematic cross-sectional view of a second example of HEMT transistor 1. The transistor 1 of FIG. 2 differs from that of FIG. 1 only by the structure of its control gate 2. As in the example of FIG. 1, the control gate 2 is positioned on the semiconductor layer 13 between the conduction electrodes 16 and 17. The control gate 2 comprises a gate oxide disposed on the semiconductor layer 13. The gate oxide is electrically insulating. The gate oxide here is devoid of a lower layer. Nanocrystals 23 are positioned directly against the semiconductor layer 13. The nanocrystals 23 are covered by an upper layer 22 of the gate oxide. A gate metal 21 is disposed on the upper layer 22. The nanocrystals 23 are also formed of electrically conductive material or semiconductor material. Nanocrystals 23 are electrically isolated from one another by the upper layer 22. The nanocrystals 23 also exhibit an electrostatic charge so that the area 15 vertically above the grid 2 and at the interface of the layers 12 and 13 is devoid of electron gas. As in the example of FIG. 1, the electrostatic charges of the nanocrystals 23 are obtained by the application of an electric field at the interface between the semiconductor layers 12 and 13 under the gate 2, so as to transit the electrons of the electron gas layer 14 to the nanocrystals 23 by tunnel effect. The tunnel effect is here facilitated by the absence of a lower layer of the gate oxide.

FIGS. 3 to 7 illustrate various steps of a method of manufacturing a transistor 1 as illustrated in FIG. 1. In FIG. 3, there is a precursor of transistor 1, comprising a substrate 11, a buffer layer not shown and disposed on the substrate 11, a first layer 12 of a type III-V semiconductor alloy disposed on the buffer layer, and a second layer 13 of a semiconductor alloy of the type III-V so as to form an electron gas 14 at the interface between the layers 12 and 13. These different layers can have the compositions, dimensions and structures as detailed above. For the sake of readability, the electron gas is illustrated as a layer 14 at the interface between the layer 12 and the layer 13. A lower insulator layer 24 is disposed on the semiconductor layer 13, at least at the level of the control gate to be formed. The insulating layer 24 is advantageously of the High K type. The insulating layer 24 is, for example, formed of Al 2 O 3. The insulating layer 24 is for example formed by epitaxy. In Figure 4, nanocrystals 23 were deposited on the upper face of the insulating layer 24. The nanocrystals 23 are here scattered. The formation of the nanocrystals 23 may comprise a physical vapor deposition of a metal, followed by an annealing step. The document `Very small-size and high-density 13-FeSi2 nanocrystal assemblies grown on Si (100) substrate using an embedded solid-phase epitaxy and bionanoprocess with protein ferritin 'published in Applied Physics Letters Volume 91, 203102 pages to 203102-3. November 2007, describes an example of a method of forming scattered nanocrystals. In FIG. 5, an upper insulating layer 22 is deposited on the nanocrystals 23 and the lower insulating layer 24. The upper insulating layer 22 is formed, for example, by a resumption of the amorphous deposit, preferably by layer deposition. atomic or ALD (for Atomic Layer 25 Deposition in English language). The upper insulating layer 22 advantageously has the same chemical composition as the lower layer 24. The upper insulating layer 22 is used to electrically isolate scattered nanocrystals 23. In FIG. 6, a gate metal 21 is deposited on the upper insulating layer 22. The gate 2 is shaped, for example by photolithography. Moreover, conduction electrodes (not shown) of the transistor 1 have also been formed on the semiconductor layer 13. At this stage, the electron gas layer 14 under the gate 2 is continuous and the transistor 1 is then normally passing type.

In FIG. 7, a bias is applied to the gate metal 21 of the gate 2. The potential on the gate metal 21 is greater than the potential applied to the conduction electrodes, so that an electric field, such as illustrated by the bias arrow, is applied on the interface between the semiconductor layers 12 and 13 and under the gate 2. When this field has a sufficient amplitude, the electrons then present at this interface under the grid 2 pass through the semiconductor layer 13 and the insulating layer 24 and then charge the nanocrystals 23, as illustrated by the arrows. Therefore, the transistor 1 has a zone free of electrons under the gate 2 at the interface 5 between the semiconductor layers 12 and 13, so that a transistor 1 of normally blocked type is formed. In the examples which are detailed previously, the layers 12 and 13 are nitrides of type III elements. Other semiconductor alloys of type III-V semiconductor alloys may also be used for layers 12 and 13. For example, it may be possible to form layers 12 or 13 with InP or GaAs.

Claims (13)

REVENDICATIONS1. A high electron mobility field effect transistor (1), comprising: first and second semiconductor layers (12, 13) superimposed to form an electron gas layer (14) at their interface; a control gate formed on the second semiconductor layer, characterized in that the control gate comprises: a first gate oxide layer; nanocrystals (23) of conductive or semiconductor material, the nanocrystals having an electrostatic charge, said nanocrystals being electrically isolated from each other by the first gate oxide layer; a gate metal (21) formed on the first gate oxide layer (22). 15 A high electron mobility field effect transistor (1) according to claim 1, wherein the relative dielectric permeability of the first gate oxide layer (22) is at least 5. 20 A high electron mobility field effect transistor (1) according to claim 2, wherein said first gate oxide layer (22) essentially contains A1203. A high electron mobility field effect transistor (1) according to any one of the preceding claims, comprising a second gate oxide layer (24) disposed between the nanocrystals (23) and the second semiconductor layer (13). ). 5. A high electron mobility field effect transistor (1) according to claim 4, wherein said first and second gate oxide layers have the same chemical composition. The field effect transistor of claims 2 and 5, wherein said first gate oxide layer (22) has a thickness greater than the second gate oxide layer (24). A field effect transistor according to claim 6, wherein said first gate oxide layer (22) has a thickness of between 6 and 20 nm and wherein said second gate oxide layer (24) 40 has a thickness between 1 and 1Onm. 3033664 A high electron-mobility field effect transistor (1) according to any one of claims 1 to 3, wherein said nanocrystals (23) are positioned at an interface between the second semiconductor layer (13) and said first optical layer. gate oxide (22). 5 A method of adjusting the threshold voltage of a high electron mobility field effect transistor, comprising the steps of: providing a high electron mobility field effect transistor (1), comprising: first and second semiconductor layers (12, 13) superimposed to form an electron gas layer (14) at their interface; a control gate (2) formed on the second semiconductor layer (13) and having; A first gate oxide layer (22); nanocrystals (23) of conductive or semiconductive material, said nanocrystals being electrically isolated from one another by the first gate oxide layer; a gate metal (21) formed on the gate oxide layer (22); -Application of an electric field on the nanocrystals (23) and on the interface between the first and second semiconductor layers, so as to generate a tunnel current between said interface and said nanocrystals. The method for adjusting the threshold voltage of claim 9, wherein said applying the electric field includes applying a potential on the gate metal higher than the potential on a conduction electrode of said high-field effect transistor. electronic mobility. 11. A method of adjusting the threshold voltage according to claim 10, wherein the potential difference between the gate metal and said conduction electrode is at least equal to 5V and at most equal to 15V. A method of adjusting the threshold voltage according to any one of claims 9 to 11, wherein said nanocrystals (23) apply an electrostatic field to the interface between said first and second semiconductor layers (12, 13) after said application of said electric field, so that said transistor (1) is then blocked in the absence of polarization applied to said gate metal (21).