FR3021430A1 - METHOD OF OBTAINING INFORMATION STORED IN MODULE REGISTERS (S) OF PROCESSING A COMPUTER JUST AFTER THE FATAL ERROR - Google Patents

Abstract

A method provides information stored in registers (R11-R4J) of at least one processing module (MT1-MTJ) of a computer (CA), each processing module (MT1-MTJ) further comprising a management controller (CG1-CGJ) capable of reading the information stored in the associated registers (R11-R4J), and a programmable logic circuit (CL1-CLJ) capable of triggering a required reset following a fatal error. To do this, if a reset request is received by a programmable logic circuit (CL2) of a processing module (MT2), this programmable logic circuit (CL2) suspends the triggering of this reset and alerts the occurrence of a fatal error the associated management controller (CG2) which, if it is able, reads the information stored in registers (R12-R42) associated and selected, then stores this information read in a file, then authorized the programmable logic circuit (CL2) associated with triggering the required reset.

Description

The invention relates to computers comprising at least one processing module comprising a management controller (FIG. 1). sometimes referred to as "service processor" or "management controller") and a programmable logic circuit (FPGA), which allows obtaining information stored in registers of different hardware components (or hardware ") of a processing module in the event of a fatal error. The term "computer" herein refers to a computer comprising one or more processing modules that can perform tasks in parallel and / or in series. Each processing module is equipped with a management controller, at least one processor, a programmable logic circuit and a memory coherence switch (such as for example a BCS2 ("Bull Coherent Switch release 2") ensuring the coherence of the memories between the different processing modules and thus making it possible to make the operating system (or OS) believe that its processing modules form a single module, For example, it could be a computer of the type of enterprise server or of a computer serving as computing node (or service) of a supercomputer.As known to those skilled in the art, when a computer (such as for example a server) falls into failure following the occurrence of a fatal error due to hardware, it is essential to know at least some information that is stored in some internal registers of some of its components just after the occurrence of this fatal error, so that to determine the source of the latter and therefore the component in error situation. This is particularly the case of the registers of the processor (s) (or CPU ("Central Processing Unit")), the programmable logic circuit (or FPGA ("Field Programmable Gate Array")) and the memory coherence switch. (or BCS ("Bull Coherent Switch")). For this type of severe error, the operating system (or OS) can not obtain information by its own internal mechanisms for error management ("ErrorHandler") because the computer is considered corrupted and must be restarted at faster before vital data is corrupted. Thus, a CPU that is the subject of a fatal error itself decides to restart (or reset or "reset") its computer, which prevents the associated operating system to take control.

This restart erases the contents of the volatile registers and thus prevents any information being obtained after it has occurred, except those stored in so-called "sticky" registers, and again in a very particular situation. The purpose of the invention is therefore notably to improve the situation, and in particular to make it possible, following the occurrence of a fatal error, to obtain information stored in certain registers of each processing module of a computer in which each processing module further comprises a management controller, able to read the information stored in the associated registers, and a programmable logic circuit capable of triggering a reset (or a "reset") required (e) following a fatal error. For this purpose, it proposes a method in which, on receipt of a reset request by a programmable logic circuit of a processing module, this programmable logic circuit suspends the triggering of this reset and alerts the occurrence of a fatal error the associated management controller which, if able, reads the information stored in associated and selected registers, then stores this information read in a file, then allows the associated programmable logic circuit to trigger this required reset .

It is thus possible to recover the contents of certain registers almost in real time, and more precisely just after the report of the occurrence of a fatal error, with a view to analyzing the cause of the latter.

The method according to the invention can comprise other characteristics that can be taken separately or in combination, and in particular: when the management controller can not read the information stored in the associated and chosen registers, the logic circuit can be authorized programmable associated with triggering the required reset, and it is possible to block an initialization phase on a synchronization point between the management controller and a basic input / output system of the processing module, then the management controller can read the information stored in associated and chosen registers, then store these information read in a file, then we can restart the computer; each management controller can choose associated registers from a list of registers that it stores; the list may comprise a first part comprising registers to be read before a reset, and a second part comprising registers to be read after a reset; in the presence of a master processing module and at least one slave processing module, when a slave processing module comprises a programmable logic circuit having received a reset request, the associated management controller may alert the controller of management of the master processing module of the occurrence of a fatal error in its slave processing module, then the management controller of the master processing module can transmit to the management controller of each processing module an authorization for synchronized reading of the information stored in associated and chosen registers and an instance name for the file in which to store this read information; the management controller of each processing module can signal the generation of its file to the management controller of the master processing module, and the management controller of the master processing module can inform each programmable logic circuit of a processing module that it is authorized to trigger a reset when it has received a file generation signaling from each management controller of a processing module, then the management controller of the master processing module can trigger a restart of the computer; before triggering the restart of the computer, the management controller of the master processing module may generate an alert message to indicate that files have been stored in each of the master and slave processing modules. The invention also proposes a computer program product comprising a set of instructions which, when executed by processing means, is suitable for implementing a control method of the type of the one presented above to obtain information stored in registers of at least one processing module of a computer following the occurrence of a fatal error. The invention also proposes a computer comprising at least one processing module comprising registers storing information, a management controller capable of reading the information stored in these registers, and a programmable logic circuit capable of triggering a reinitialization required following an error. fatal. In the event of reception of a reset request by a programmable logic circuit of a processing module, this programmable logic circuit is arranged to suspend the triggering of this reset and to alert the controller of the occurrence of a fatal error. associated with it, and the latter is arranged, if it is able, to read the information stored in associated and selected registers, then to store this information read in a file, before the associated programmable logic circuit is allowed to trigger the required reset. For example, when the management controller can not read the information stored in the associated and selected registers, the associated programmable logic circuit can be arranged, if allowed, to trigger the required reset, and this management controller can be arranged, following a blocking of an initialization phase on a synchronization point between it and an elementary input / output system of its processing module, to read the information stored in associated and chosen registers, then to store this information read in a file.

Other characteristics and advantages of the invention will appear on examining the following detailed description, and the accompanying drawings, in which: FIG. 1 schematically and functionally illustrates a computer with processing modules according to FIG. invention, and - Figure 2 illustrates an example of an algorithm implementing a method of obtaining information according to the invention. The object of the invention is in particular to propose a method for obtaining information stored in registers Rij of at least one processing module MTj of a computer CA following the occurrence of a fatal error. In what follows, by way of non-limiting example, the CA computer is an enterprise server. But the invention is not limited to this type of computer. It concerns indeed any computer system comprising one or more processing modules that can perform tasks in parallel and / or in series. Thus, it may also be a computer used as computing node (or service) of a supercomputer. FIG. 1 schematically illustrates a non-limiting example of a computer CA, here a server, comprising J processing modules MTj (j = 1 to J). For example, J is 8. But J can take any value greater than or equal to one. Of these J processing modules MTj, one of them is called master, while the other J-1 are called slaves. Each processing module MTj comprises at least Rij registers storing information, a management controller CGj, able to read the information that is stored in these registers Rij, a programmable logic circuit (or FPGA ( Field Programmable Gate Array ")) CLj, capable of triggering a reset (or" reset ") which has been required following the occurrence of a fatal error due to a hardware (or" hardware "), an elementary input system / output (or BIOS ("Basic Input Output System") - here not shown), memories (not shown), and at least one processor (or CPU ("Central Processing Unit") P1j or P2j. Note that when the computer CA comprises several processing modules MTj, as shown in Figure 1, each of these (MTj) also includes a memory coherence switch CMj (as for example a BCS2 ("Bull Coherent Switch release 2" ) which ensures the coherence of the memories between the different processing modules MTj and thus makes it possible to make the operating system (or OS) believe that its processing modules MTj form a single module In other words, each coherency switch memory CMj makes it possible to offer coherent access to any memory of any processing module MTj from any processor P1J, P2j of any processing module MTj. provides a so-called SMC function ("Satellite Management Controller") that manages access to the hardware of its processing module MTj, such as for example the reading of a processor register P1j or P2j or CMj memory coherence switch or access to a temperature sensor. The management controller CG1 MT1 master processing module provides, in addition to a management controller CGj '(j' # 1) of a slave processing module MTj ', a function called BMC ("Baseboard Management Controller") which manages especially the "power off" and ignitions ("power on") of the CA computer, the resets (or "resets"), the read permissions of registers Rij, and the inter-module synchronization of MTj treatment.

It will also be noted that the registers Rij of each processing module MTj, which are concerned by the invention (and therefore in which information must be recovered in the event of a fatal error), form part of the programmable logic circuit CLj (here R1j) , each processor (here R2j and R3j), and the memory coherence switch CMj (here R4j).

Within each processing module MTj, the communications between the management controller CGj and the memory coherence switch CMj can be done via an interface I2C, the communications between the processors P1j and P2j and the memory coherence switch CMj can take place via a QIP interface ("Quick Path Interconnect"), the communications between the management controller CGj and the processors P1 j and P2j can be done via a PECI interface, and the communications between the management controller CGj and the programmable logic circuit CLj can be done via an xbus interface. Furthermore, the communications between the memory coherence switches CMj of the different processing modules MTj can be done via an XQPI type communication network ("eXtended QPI"), and the communications between the management controllers CGj of the different processing modules MTj can be done via an Ethernet network. As indicated above, the invention proposes a method for obtaining information stored in registers Rij of each processing module MTj of a computer CA.

This method can be implemented by a computer CA according to the invention, whenever a programmable logic circuit CLj of a processing module MTj receives a request to reset (or reset) a processor P1 j, P2j or the memory coherence switch CMj following the occurrence of a fatal error. According to this method, when the aforementioned situation occurs, the programmable logic circuit CLj concerned suspends the triggering of the required reset and warns of the occurrence of a fatal error the management controller CGj associated with it within its processing module MTj . Then, if this management controller CGj is able to do so (that is to say, has the possibility), it reads the information that is stored in associated and selected Rij registers of its processing module MTj, then stores this information read in a file. Then, the programmable logic circuit CLj, which received the reset request, is allowed to trigger the required reset (and that it has been suspended pending instructions).

The readability of a management controller CGj depends above all on the technical possibility of accessing the registers Rij at the moment considered, as well as possibly of the reception of a reading authorization.

It is important to note that, when the computer CA comprises several processing modules MTj, including a master MT1 and at least one slave MTj ', and a slave processing module MTj' comprises a programmable logic circuit (slave) CLj ' having received a reset request, the associated slave management controller CGj 'can alert the management controller (master) CG1 of the master processing module MT1 of the occurrence of a fatal error in its slave processing module MTj'. Then, the master management controller CG1 can transmit to the management controller CGj of each processing module MTj (j = 1 to J) a synchronized read authorization of the information stored in associated and selected Rij registers and an instance name for the file in which to store this read information. This file is stored in a non-volatile memory (for example of the flash type) of the management controller CGj. In other words, it is the master management controller CG1 that supervises and authorizes the reading of selected registers in each of the MT1 master processing module and MTj 'slave. This option is intended to retrieve the information stored in all the useful reg registers of all MTj processing modules, including those that have not seen the fatal error, in order to know the origin of the problem. Indeed, transactions circulate between processing modules MTj and therefore a fatal error can be detected by a "consumer" processing module while the fatal error comes from a "transmitter" processing module, and therefore all the controllers management CGj must be notified that there has been a fatal error in the CA computer so that they retrieve the information stored in their respective registers Rij. Note however that when a fatal error occurs, it can spread from chip to chip and processing module MTj processing module MTj '. Consequently, it may happen that this fatal error triggers others in a burst mechanism in the same processing module MTj, and in this case it is necessary to avoid performing readings of registers Rij in "cascades". Preferably, each management controller CGj signals the generation of its file to the master management controller CG1, then the latter (CG1) informs each programmable logic circuit CLj that it is authorized to trigger a reset (or reset) if it has received a file generation signaling of each management controller CGj. Then, the master controller CG1 can trigger a restart (or "reboot") of the CA calculator.

Note that before triggering this restart of the CA computer, the master management controller CG1 may generate an alert message to signal to a person responsible for the CA computer that files relating to the occurrence of a fatal error have have been stored in each of the master and slave MTj processing modules. These files can then be downloaded to a computer and analyzed using a diagnostic tool. It will also be noted that it may happen that a management controller CGj can not read the information that is stored in the associated and selected Rij registers, for example after having received the possible authorization from the master management controller CG1. This situation can for example arise in certain situations of particularly serious fatal error when a management controller CGj no longer has access to the processors P1j and P2j and / or the memory coherence switch CMj because their access bus (PECI and I2C) are blocked.

In the latter case, it is first possible to allow the programmable logic circuit CLj which is associated with this management controller CGj to trigger the required reset (or reset), and it is possible to block an initialization phase on a synchronization point. between this management controller CGj and the basic input / output system (or BIOS) of its processing module MTj. This reset has the effect of unblocking the data buses and thus allowing the management controller CGj to access again the processors P1j and P2j and the memory coherence switch CMj, and the blocking of the BIOS immediately after this reset makes it possible to avoid that its boot corrupt the contents of the sticky registers. It will be understood that in this case only the sticky registers will be read, since all the other registers will have been reset to their values after reset (generally zero) while these sticky registers keep their values before reset. The information retrieved in this case will be less complete but may nevertheless be sufficient in many situations. Then, the management controller CGj can read the information that is stored in associated and selected Rij registers of its processing module MTj, possibly after being authorized to do so by the master management controller CG1. In fact, only the so-called "sticky" type registers can be read without fear of having been corrupted by the reset that has just occurred. Then, this management controller CGj can put this information read in a file that stores in a non-volatile memory (for example flash type). Finally, we can restart the CA computer by performing a procedure called "power cycle") of turning off the computer CA and then turn it on again to reset the sticky type registers to their respective default values. This procedure is useful after a fatal error because the consistency of the content of the sticky registers is not ensured. For example, this restart can be triggered by the master controller CG1. In order to speed up the reading of the registers Rij, each management controller CGj can choose the registers Rij that it is authorized to read in its processing module MTj from a list of registers that it stores in a non-volatile memory. For example, this list may comprise a first part comprising registers that must be read before a reset (or reset) has been performed, and a second part comprising registers that must be read after a reset (or reset). has been done. The registers of this first part essentially belong to the processors P1j and P2j and to the programmable logic circuit CLj (the latter contains in particular important information which indicates which is the first fatal error that has occurred in the computer CA (which processor or which switch of memory coherence CMj of which processing module MTj)). The registers of this second part are essentially of the sticky type, and therefore belong to the memory coherence switches CMj and the processors P1j and P2j (these are, for example, CSR ("Control and Status Register") registers with addressing "Bus / Device / function"). Note that the first part of the list can be optionally and advantageously subdivided into sub-parts associated with the different types of processors P1j, P2j and programmable logic circuit CLj (error registers with addressing "Page / Offset"). For example, a sub-part may be dedicated to MSR ("Model Specific Register") type registers in "Offset + CorelD" addressing of one type of processor, and another sub-part may be dedicated to CSR type registers. with "Bus / Device / function" addressing of another type of processor. When this option exists, each management controller CGj begins by determining the type of the processor to which it must address, then it selects the subpart of the first part of the list that is associated with this type of processor. This makes it possible to have the same program in each management controller CGj regardless of the type (s) of processor (s) that includes its processing module MTj. FIG. 2 schematically illustrates an example of an algorithm implementing an exemplary method for obtaining information according to the invention. This algorithm comprises a step 10 in which a slave programmable logic circuit CLj '(for example CL2) receives a reset request (or reset) because of the occurrence of a fatal error in its slave processing module MT2, and consequently suspends the triggering of this reset. The algorithm continues with a step 20 in which the slave programmable logic circuit CL2 alerts of the occurrence of a fatal error the associated management controller CG2. Then, the latter (CG2) alerts the master controller CG1 of the occurrence of a fatal error in its MT2 slave processing module. Then, in a step 30, the master management controller CG1 transmits to each of the management controllers CG1 to CGJ a synchronized read authorization of the information which is stored in associated and selected registers Rij of their processing modules MT1 to MTJ respectively, as well as an instance name for the files in which they will store the information they have read. Then, in a step 40, each management controller CGj (j = 1 to J) determines whether it is possible to read the information that is stored in associated and selected Rij registers (for example those predefined from the first group of the list stored). If not, a step 60 is carried out. On the other hand, if so, a step 50 is performed in which each management controller CGj reads the information that is stored in the associated and selected registers Rij, then stores this information read in a file having the instance number provided by the master management controller CG1, then signaling the generation of its file to the master management controller CG1.

Then, in a step 60, the master management controller CG1 performs a test to determine whether it has received the J files of J processing modules MTj. In the negative, a step 110 is performed which will be described later. If so, a step 70 is performed in which the master management controller CG1 informs each programmable logic circuit CLj (whether slave or master) that it is authorized to trigger a reset (or reset) of its processing module. MTj. Then, in a step 80, each slave programmable logic circuit CLj (whether slave or master) triggers a reset (or reset) of its processing module MTj.

Then, in a step 90, the master management controller CG1 generates an alert message intended to signal to a person responsible for his computer CA that files relating to the occurrence of a fatal error have been stored in each of the modules of MTj master and slave processing (s). Then, in a step 100, the master management controller CG1 triggers a reboot (or "reboot") of the AC power cycle computer. When the test performed in step 60 is negative, and therefore at least one register Rij could not be read in at least one processing module MTj, a step 110 is performed in which the management controller master CG1 informs each programmable logic circuit CLj (whether slave or master) that it is authorized to trigger a reset (or reset) of its processing module MTj.

Then, in a step 120, each programmable logic slave CLj (whether slave or master) triggers a reset (or reset) of its processing module MTj in order to unblock the data buses.

Then, in a step 130, each management controller CGj (whether slave or master) blocks the initialization phase on a synchronization point between it (CGj) and the elementary input / output system (or BIOS). of its MTj processing module in order to prevent the boot of the BIOS from corrupting the contents of the sticky registers.

Then, in a step 140, the master management controller CG1 transmits to each of the management controllers CG1 to CGJ a synchronized read authorization of the information which is stored in associated and selected registers Rij of their processing modules MT1 to MTJ respectively, as well as an instance name for the files in which they will store the information they have read. Then, in a step 150 each management controller CGj reads the information which is stored in the associated and selected Rij registers (for example those of the second group of the stored list), then stores this information read in a file having the number of an instance provided by the master management controller CG1, then reports the generation of its file to the master management controller CG1. Then, the steps 90 and 100 described above are carried out. Note that the invention can also be considered in the form of a computer program product comprising a set of instructions which, when executed by processing means of a computer CA, is adapted to implement a control method of the type described above is used to obtain information stored in registers Rij of at least one processing module MTj of the computer CA following the occurrence of a fatal error.

The invention is not limited to the information acquisition method and computer embodiments described above, only by way of example, but it encompasses all the variants that may be considered by those skilled in the art within the scope of the claims below.

Claims (10)

REVENDICATIONS1. Method for obtaining information stored in registers (Rij) of at least one processing module (MTj) of a computer (CA), each processing module (MTj) further comprising a management controller (CGj) adapted to read the information stored in the associated registers (Rij), and a programmable logic circuit (CLj) capable of triggering a reset required following a fatal error, characterized in that in case of reception of a reset request by a programmable logic circuit (CLj) of a processing module (MTj), this programmable logic circuit (CLj) suspends the triggering of this reset and alerts the occurrence of a fatal error the associated management controller (CGj) which, if able, reads the information stored in associated and selected registers (Rij), then stores this read information in a file, and then authorizes said associated programmable logic circuit (CLj) to trigger said reset required. 2. Method according to claim 1, characterized in that when said management controller (CGj) can not read the information stored in said associated registers (Rij) and selected, said associated programmable logic circuit (CLj) is allowed to trigger said reset required, and an initialization phase is blocked on a synchronization point between said management controller (CGj) and an elementary input / output system of said processing module (MTj), then said management controller (CGj) reads the information stored in associated registers (Rij) and selected, then stores this information read in a file, then restarting said computer (CA). 3. Method according to one of claims 1 and 2, characterized in that each management controller (CGj) chooses associated registers (Rij) from a list of registers it stores. 4. Method according to claim 3, characterized in that said list comprises a first part comprising registers to be read before a reset, and a second part comprising registers to be read after a re-initialization. 5. Method according to one of claims 1 to 4, characterized in that in the presence of a processing module (MT1) master and at least one processing module (MTj ') slave, when a module of processing (MTj ') slave comprises a programmable logic circuit (CLj') having received a reset request, the associated management controller (CGj ') alerts the management controller (CG1) of said processing module (MT1) master of the occurrence a fatal error in its processing module (MTj ') slave, then said management controller (CG1) of the processing module (MT1) master transmits to the management controller (CGj) of each processing module (MTj) authorization synchronized reading information stored in registers associated (Rij) and selected and an instance name for the file in which it must store this information read. 6. Method according to claim 5, characterized in that the management controller (CGj) of each processing module (MTj) reports the generation of its file audit management controller (CG1) of the processing module (MT1) master, and said management controller (CG1) of the master processing module (MT1) informs each programmable logic circuit (CLj) of a processing module (MTj) that it is authorized to trigger a reset when it has received generation signaling file of each management controller (CGj) of a processing module (MTj), then said management controller (CG1) of the processing module (MT1) master triggers a restart of said computer (CA). 7. Method according to one of claims 5 and 6, characterized in that before triggering said restart of the computer (CA), said management controller (CGj) of the processing module (MTj) master generates an alert message to indicate that files have been stored in each of said processing modules (MTj) master and slave (s). 8. Computer program product comprising a set of instructions which, when executed by processing means, is adapted to implement the method according to one of the preceding claims to obtain information stored in registers ( Rij) of at least one processing module (MTj) of a computer (CA) following a fatal error. 9. Computer (CA) comprising at least one processing module (MTj) comprising registers (Rij) storing information, a management controller (CGj) capable of reading the information stored in said registers (Rij), and a logic circuit programmable (CLj) capable of triggering a reset required following a fatal error, characterized in that in case of reception of a reset request by a programmable logic circuit (CLj) of a processing module (MTj), this programmable logic circuit (CLj) is arranged to suspend the triggering of this reset and to alert of the occurrence of a fatal error said associated management controller (CGj), and the latter (CGj) is arranged, if it is authorized , to read the information stored in associated and selected registers (Rij), and then to store this read information in a file, before said associated programmable logic circuit (CLj) is allowed to trigger said required reset. 15 10. Calculator according to claim 9, characterized in that, when said management controller (CGj) can not read the information stored in said associated registers (Rij) and chosen, said programmable logic circuit (CLj) associated is arranged, s it is authorized, to trigger said required reset, and said management controller (CGj) is arranged, following a blocking of an initialization phase on a synchronization point between this management controller (CGj) and a elementary input / output system of its processing module (MTj), for reading the information stored in associated registers (Rij) and chosen, and then for storing this information read in a file.