FR3010822B1 - Circuit a memoire comprenant des moyens de detection d'une injection d'erreur - Google Patents

Circuit a memoire comprenant des moyens de detection d'une injection d'erreur

Info

Publication number
FR3010822B1
FR3010822B1 FR1358926A FR1358926A FR3010822B1 FR 3010822 B1 FR3010822 B1 FR 3010822B1 FR 1358926 A FR1358926 A FR 1358926A FR 1358926 A FR1358926 A FR 1358926A FR 3010822 B1 FR3010822 B1 FR 3010822B1
Authority
FR
France
Prior art keywords
detecting
memory circuit
error injection
error
injection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1358926A
Other languages
English (en)
Other versions
FR3010822A1 (fr
Inventor
Sebastien Faivre
Alami Salwa Bouzekri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Inside Secure SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inside Secure SA filed Critical Inside Secure SA
Priority to FR1358926A priority Critical patent/FR3010822B1/fr
Priority to EP14796156.9A priority patent/EP3047486A1/fr
Priority to PCT/FR2014/052217 priority patent/WO2015040304A1/fr
Publication of FR3010822A1 publication Critical patent/FR3010822A1/fr
Application granted granted Critical
Publication of FR3010822B1 publication Critical patent/FR3010822B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
FR1358926A 2013-09-17 2013-09-17 Circuit a memoire comprenant des moyens de detection d'une injection d'erreur Active FR3010822B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1358926A FR3010822B1 (fr) 2013-09-17 2013-09-17 Circuit a memoire comprenant des moyens de detection d'une injection d'erreur
EP14796156.9A EP3047486A1 (fr) 2013-09-17 2014-09-08 Circuit a mémoire comprenant des moyens de détection d'une injection d'erreur
PCT/FR2014/052217 WO2015040304A1 (fr) 2013-09-17 2014-09-08 Circuit a mémoire comprenant des moyens de détection d'une injection d'erreur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1358926A FR3010822B1 (fr) 2013-09-17 2013-09-17 Circuit a memoire comprenant des moyens de detection d'une injection d'erreur

Publications (2)

Publication Number Publication Date
FR3010822A1 FR3010822A1 (fr) 2015-03-20
FR3010822B1 true FR3010822B1 (fr) 2015-10-02

Family

ID=50023667

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1358926A Active FR3010822B1 (fr) 2013-09-17 2013-09-17 Circuit a memoire comprenant des moyens de detection d'une injection d'erreur

Country Status (3)

Country Link
EP (1) EP3047486A1 (fr)
FR (1) FR3010822B1 (fr)
WO (1) WO2015040304A1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1734536A1 (fr) * 2005-06-15 2006-12-20 STMicroelectronics SA Mémoire protégée contre des attaques par injection d'erreur dans des signaux de sélection de cellules mémoire
WO2008093257A2 (fr) * 2007-01-30 2008-08-07 Nxp B.V. Procédé de protection contre les attaques et circuit apparenté
US8560899B2 (en) * 2010-07-30 2013-10-15 Infineon Technologies Ag Safe memory storage by internal operation verification

Also Published As

Publication number Publication date
EP3047486A1 (fr) 2016-07-27
FR3010822A1 (fr) 2015-03-20
WO2015040304A1 (fr) 2015-03-26

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