FR3010795A1 - INTEGRATED CIRCUIT COMPRISING AN ELECTRONIC CIRCUIT AND A CIRCUIT FOR MONITORING THE ELECTRONIC CIRCUIT - Google Patents

Abstract

Integrated circuit (1) comprising an electronic circuit (2) and a monitoring circuit (3) of said electronic circuit (2) configured to emulate a critical path of the electronic circuit (2). The monitoring circuit (3) comprises a clock input (5) for receiving the clock signal (H) delivered to the electronic circuit (2), a configurable delay chain (6) having logical components, and having a channel input connected to the clock input (5) and a channel output capable of delivering a delayed clock signal (H +), and a control loop (8) configured to select a logic circuit representative of the critical path one set of reference logic circuits from the clock signal (H), the delayed clock signal (H +) and the operating conditions (P, V, T) of the electronic circuit (2) and to output a configuration signal to the delay chain (6) for configuring said selected logic circuit.

Description

The invention relates to integrated circuits, in particular the monitoring of an electronic circuit, for example a processor. There are several solutions to prevent defective time drift of an electronic circuit such as a processor, and to optimize the operation thereof. One of them is to "monitor", that is to say monitor, the signal transmission performance of the critical path of the processor. The critical path is the longest electrical path between two flip-flops of the processor, i.e., having the longest transmission time. Generally, to achieve an electronic critical-path performance monitoring, several electronic paths of the processor likely to be critical for the operation of the integrated circuit are identified during the design of the integrated circuit. Each electronic component is associated with a signal transmission time and thus each critical path has a certain signal transmission time. The signal transmission time is then monitored from a time monitoring circuit arranged on the integrated circuit. During the life of the integrated circuit, the signal transmission has a tendency to degrade and the transmission time consequently increases. When a time monitoring circuit detects a time drift, it is possible to anticipate faulting of the processor by controlling the operating parameters of the processor to overcome this drift, for example by adjusting the frequency of the clock signal, the voltage of the power supply of the integrated circuit, or even the bias voltage of the transistors of the integrated circuit. There are known different types of critical path monitoring sensors. Critical path replication systems, criticalpath replica, use a critical path replica for some parameter values. These systems allow a facilitated measurement of the transmission time but are effective only if there is only one possible critical path, and if the possible parameter variations are very limited. These systems are not usable therefore for integrated circuits having substantial processors with a large number of possible critical paths. The emulated critical path emulators use a look-up table, pre-filled to record transmission rate matches with the logic circuit and possible interconnections, and a monitor. to select a critical path from the parameters and the lookup table. Emulators are more accurate than conventional critical path reproduction systems, and can adapt to different operating conditions of the integrated circuit from the look-up table. But to obtain good performance emulators, the circuits emulating the critical paths are extremely simplified and do not exactly represent the critical paths of the processor. Moreover, these emulators generally require the storage of a large number of correspondence tables and this results in the use of a memory or bank register of significant size. The so-called "representative critical path" systems are based on the spatial correlation property between the parameters making it possible to construct the test structure, and make it possible to synthesize a critical path in a statistical manner. These systems have a high accuracy with respect to correlation variations and are of relatively small physical size on the integrated circuit. However, they do not allow taking into account the operating conditions of the integrated circuit such as the supply voltage, the operating temperature and the operating mode of the transistors. The integrated oscillators, or "on-chip ring oscillators" in English, are used in large numbers on an integrated circuit to measure the variations of the parameters of the processor of the integrated circuit and to determine the effects of the critical paths from a spatial correlation. However, for a medium-sized integrated circuit, one hundred integrated oscillators are needed. Another known example of a critical path monitoring sensor includes a delay chain that makes it possible to perform an approximate replica of the critical path of the processor. For this, the delay chain comprises five typical different logic circuits. Depending on the operating conditions of the integrated circuit, one of the five circuits is chosen to represent the replica of the critical path of the processor during operation. In such a system, not only the five logic circuits made in the sensor occupy a certain physical space in the sensor, and therefore on the integrated circuit, but since there are only five choices of critical path replicas, the accuracy of the replica is limited. According to one embodiment, there is provided a monitoring sensor of an electronic circuit for finely adjusting the critical path in particular from multiple combinations of logic gates.

It is also proposed a delay measuring device over a wider range with greater accuracy around the period of the integrated circuit clock signal. According to a first aspect, there is provided an integrated circuit comprising an electronic circuit and a monitoring circuit of said electronic circuit, the monitoring circuit being configured to emulate a critical path of the electronic circuit. According to a general characteristic, the monitoring circuit comprises: a clock input for receiving the clock signal delivered to the electronic circuit; a configurable delay chain comprising logic components and having a channel input connected to the input; clock and a chain output adapted to deliver a delayed clock signal, and a control loop configured to select a logic circuit representative of the critical path from a set of logic reference circuits from the clock signal, the delayed clock signal and operating conditions of the electronic circuit and for outputting a configuration signal to the delay chain to configure said selected logic circuit. Since the monitoring circuit, or critical path sensor, is mounted on the integrated circuit on which the electronic circuit, or processor, is coupled, it is subjected to the same environmental conditions, that is to say to the same operating conditions as the processor. It is configured to receive inter alia the same clock signal, the same supply voltage signal, and the same bias voltage of the transistors. It is also previously configured so that the transistors are in the same operating mode as those of the processor. The operating mode of the transistors is referenced with respect to the NMOS transistors and the PMOS transistors, which can each have a slow (fast in English), fast (fast in English), or normal (typical in English) operation. The transistors can thus be configured according to the following modes: Slow-Slow, or Slow-Fast, or Typical-Typical, or Fast-Slow, or Fast-Fast. Thus, if operating conditions, such as operating temperature or supply voltage, change even slightly for the processor, these conditions also change for the critical path sensor. The operating conditions of the processor such as the supply voltage and the operating temperature are measured by means of separate dedicated sensors. These sensors make it possible to provide a rough measurement of some of the operating conditions of the processor, and therefore of the integrated circuit, to the control loop.

The control loop has been previously configured using a correspondence table, to associate a logic circuit representing a critical path at least according to the operating conditions received.

For the same combination of coarse operating condition values obtained from a temperature sensor and an external voltage sensor, for example, there is a plurality of possible reference logic circuits. The control loop is configured to select a logic circuit from the set of reference logic circuits for the given operating conditions. The selection of the logic circuit from the set of reference logic circuits is refined according to the clock signal and the delayed clock signal, and in particular as a function of the delay between the two signals.

Preferably, the delay chain comprises a set of logic components and arrangement means able to combine at least a part of said logic gates to produce the logic circuit selected by the control loop. The arrangement of the delay chain makes it possible to produce a large number of different logic circuits since it comprises a set of logic components, such as logic gates, which can be combined as a function of the logic circuit selected by the control loop. Preferably, the monitoring circuit comprises measurement means able to determine the time delay between the clock signal and the delayed clock signal, and the control loop comprises a comparison module able to compare the measured delay with minus a measurement threshold, the comparison module being coupled to an input of a selection module configured to select said logic circuit according to the operating conditions and the output signal of the comparison module. The value of the measured delay can be outputted to a circuit of parameterization of the integrated circuit to adjust the operating parameters of the integrated circuit in case of significant time drift for example. The measured delay is also transmitted to the control loop so as to adjust as necessary the combination of logic components embodying the logic circuit emulating the critical path. Indeed, the measured delay makes it possible to measure the operating conditions of the integrated circuit more finely than the external temperature and supply voltage sensors. More specifically, for a delay measured at given coarse operating conditions, measured by the external sensors, the control loop is configured to determine in the set of reference logic circuits for given coarse operating conditions, the one or more Critical paths most sensitive to refined operating conditions due to the measured delay. The control loop thus restricts the set of reference logic circuits as a function of the measured delay and the coarse operating conditions measured by the external sensors. A logic circuit emulating the critical path of the restricted group is selected for the delay chain, so as to perform a new delay measurement. Since the new logic circuit selected is more sensitive to the operating conditions than the previous one, the measured delay may differ from the previous one, so that by comparing the new measured delay to the same thresholds, the control loop can modify the selected logic circuit again. times or not. The logic circuit is thus modified as long as the measured delay differs from the preceding one by a value greater than one of the thresholds. According to one embodiment, the measuring means may comprise a digital time converter capable of measuring the delay and converting the delay into a thermometric code, and the thresholds of the comparison module of the control loop are threshold thermometric codes.

The time-to-digital converter can advantageously comprise logic means able to measure said delay with a finer precision around the value of the period of the clock signal of the electronic circuit and a coarser precision at values further away from the period of the clock signal of the electronic circuit. Since the accuracy of the measurement varies with the amplitude of the measured delay, the time-to-digital converter makes it possible to measure a delay over a longer time range for a given accuracy. Preferably, the logic means of the time-to-digital converter comprise a first logic circuit coupled to the input of the clock signal and a second logic circuit coupled to the input of the delayed signal coming from the delay chain, the first and the second second logic circuits each comprising logic gates, each logic gate of the first circuit delivering the signal with a given delay with respect to each logic gate of the second logic circuit. Since the time delay is the same for each logic gate, it is thus very easy to estimate the delay measured from the thermometric code. Advantageously, the delay chain may comprise a plurality of multiplexers, each multiplexer comprising a plurality of logic components coupled at the input so as to offer several possible logical combinations.

The use of multiplexers in the delay chain makes it possible to combine groups of logical components, and easily combines the number of logical components desired in each group from the control of the multiplexers. A multiplexer may be coupled to a plurality of logic gates of the same type such as OR gates, or NAND gates for example. Preferably, the operating conditions of the electronic circuit comprise at least the voltage imposed on the terminals of the electronic circuit, the temperature of the electronic circuit, and the operating mode of the transistors of the electronic circuit.

According to a second aspect, a method of emulating the critical path of an electronic circuit of an integrated circuit is proposed in one embodiment, the method comprising: a) a reception of the clock signal delivered to the circuit electronic, b) a transmission of a delayed clock signal by a configurable delay chain having logic components and receiving the input clock signal, c) a reception of the operating conditions of the electronic circuit, d) a selection a logic circuit representative of the critical path among a set of reference logic circuits from the clock signal, the delayed clock signal and the operating conditions of the electronic circuit, and e) a configuration of the delay chain to realize the selected logic circuit. Advantageously, the delay chain realizes the selected logic circuit from a combination of at least a part of a set of logical components.

Preferably, the time delay between the clock signal and the delayed clock signal is measured, and the measured delay is compared with at least one threshold, the selection of the logic circuit being performed as a function of the operating conditions and the result of said comparison.

Steps a) to e) are preferably reiterated, the selected logic circuit remaining unchanged as long as the operating conditions are the same and the measured delay is in the same delay interval as the measured delay before, a delay interval being defined by at least one of the thresholds.

Advantageously, said delay is measured with a finer precision around the value of the period of the clock signal of the electronic circuit and a coarser precision at values further from the period of the clock signal of the electronic circuit.

In order to measure the delay, the propagation of the clock signal with respect to the propagation of the delayed clock signal can be steadily delayed, the propagation line of the clock signal comprising logical components delivering a signal with a given delay in relation to the delay. to the logic gates of the propagation line of the delayed clock signal. Advantageously, a part of the set of logic components can be combined by means of multiplexers, each multiplexer comprising a plurality of logic gates coupled in input so as to offer several possible combinations. Other advantages and characteristics of the invention will appear on reading the detailed description of an example embodiment and implementation, not limiting, and drawings in which: - Figure 1 schematically shows an integrated circuit comprising an electronic circuit and a monitoring circuit according to one embodiment; FIG. 2 schematically illustrates in more detail the monitoring circuit of the integrated circuit of FIG. 1; FIG. 3 illustrates a flowchart of a method for configuring the control loop of the monitoring circuit of the integrated circuit of FIG. 1; FIG. 4 schematically represents an example of a delay chain according to one embodiment of the monitoring circuit of FIG. 2; FIG. 5 schematically shows an example of a time-to-digital converter according to an embodiment of the monitoring circuit of FIG. 2; FIG. 6 presents a flowchart of a method of emulation of the critical path of an electronic circuit of an integrated circuit according to an implementation mode. FIG. 1 schematically shows an integrated circuit 1 comprising an electronic circuit 2, a monitoring circuit 3 of the electronic circuit 2, a clock 4, and a parameterization circuit 30 able to adjust the operating parameters of the electronic circuit 2. In this illustrated example, the electronic circuit 2 is a processor. The electronic circuit 2 could be a PLL, or any other electronic circuit. The monitoring circuit 3 is configured to emulate a critical path of the electronic circuit 2 from the operating conditions of the integrated circuit 1, and in particular of the electronic circuit 2 of the integrated circuit 1, of the clock signal H delivered to the electronic circuit 2 and to the monitoring circuit 3 and a delayed clock signal H + shown in Figure 2. In Figure 2 is shown schematically in more detail the monitoring circuit 3 of the integrated circuit 1 of Figure 1.

The monitoring circuit 3 comprises a clock input 5 for receiving the clock signal H delivered by the clock 4, a configurable delay chain 6 having a channel input connected to the clock input 4 and an output of a chain capable of delivering a delayed clock signal H +, measuring means 7 for the delay between the clock signal H and the delayed clock signal H +, and a control loop 8 comprising a first input for receiving the value the delay measured by the measuring means 7, a second input adapted to receive the operating conditions, referenced P, V, T, of the electronic circuit 2, and an output connected to the configurable delay chain 6. An example of a configurable delay chain 6 according to an embodiment of the monitoring circuit 3 is detailed further on the support of FIG. 4. In this example, the measurement means 7 comprise a time-digital converter whose operation is 5. The control loop 8 comprises a receiving module 9 of the operating conditions P, V, T of the electronic circuit 2, a selection module 10 of a logic circuit, and a comparison module 11. The control loop 8 is configured to select a logic circuit representative of the critical path from a set of reference logic circuits from the measured delay and the operating conditions P, V, T of the electronic circuit 2 and for outputting a configuration signal to the delay chain 6 to configure the selected logic circuit. For this purpose, the control loop 8 has been parameterized from a correspondence table previously produced from a configuration method illustrated in FIG. 3.

FIG. 3 is a flowchart of a method for configuring the control loop 8 of the monitoring circuit 3 of the integrated circuit 1 of FIG. 1. The configuration method comprises a first step 300 in which a combination of operating conditions P, V, T from the possible values and states for each of the operating conditions P, V, T. The operating mode P of the transistors is referenced with respect to the NMOS transistors and to the PMOS transistors of the electronic circuit 2, which can each have a slow operation (slow in English), fast (fast in English), or normal (typical in English). The operating mode P of the transistors, commonly called process centering, can be set according to the following configurations: Slow-Slow, or Slow-Fast, or Typical-Typical, or Fast-Slow, or Fast-Fast.

The values of the supply voltage V of the electronic circuit 2 can be taken between 0.7 V and 1.2 V, and the values of the temperature T of the electronic circuit can be considered between -40 ° C and + 125 ° C. . The voltage values depend on the technology chosen to design the circuit.

In the following steps 310, 320 and 330, the variations of the delay generated respectively by a modification of the operating mode condition P or process centering of the transistors by a modification of the supply voltage V of the electronic circuit are identified. 2, and by a variation of the temperature T where is the electronic circuit 2. In respective subsequent steps 340, 350 and 360, a potential combination of logic components is selected for each new combination of operating conditions P, V, T Then, in a final step 370, a correspondence table is established in which a logic circuit is associated with a combination of operating conditions P, V, T fines. The prior configuration of the control loop 8 according to the method of FIG. 3 allows operation of the modules 9, 10 and 11 of the control loop 8 as described below with reference to FIG. Referring now again to FIG. 2, it can be seen that the receiving module 9 has an input coupled to operating condition sensors of the electronic circuit 2. The operating conditions of the electronic circuit 2 measured using a sensor correspond to the supply voltage V and the operating temperature T. These parameters are measured using separate dedicated sensors. These sensors make it possible to provide a rough measurement of these operating conditions of the electronic circuit 2, and therefore of the integrated circuit 1, to the control loop 8. A third operating condition P corresponding to the operating mode, or process centering, of the transistors of the electronic circuit 2 is also received by the reception module 9 and taken into account by the control loop 8. The comparison module 11 receives as input the signal corresponding to the delay measured by the measuring means 7. The value of the delay as well as measured is compared to at least one threshold. For example, the comparison module 11 can compare the measured delay with four thresholds of increasing value. The four thresholds define in this case five delay intervals in which the delay can be located. The first interval, for which the measured delay is smaller than the first threshold which has the smallest value, corresponds to a very small delay with respect to the clock signal.

The selection module 10 receives as input, on the one hand, the operating conditions of the electronic circuit 2 delivered by the receiving module 9, and on the other hand, the interval in which the measured delay is located. From the data received at the input, the selection module 10 determines a logic circuit that the delay chain 6 must reproduce in order to emulate the critical path of the electronic circuit 2 corresponding to the operating conditions. The selection module 10 of the control loop 8 is previously configured using a correspondence table, to associate a logic circuit representing a critical path at least according to the operating conditions received. The selection of the logic circuit from the set of reference logic circuits is refined according to the clock signal and the delayed clock signal, and in particular as a function of the delay between the two signals. The monitoring circuit 3 being mounted on the integrated circuit 1 on which the electronic circuit 2 is coupled, it is subjected to the same environmental conditions, ie to the same operating conditions as the electronic circuit 2. The delay chain 6 of the monitoring circuit 3 receiving the same clock signal H as the electronic circuit 2, if one of the operating conditions P, V, T of the electronic circuit 2, such as the operating temperature T or the supply voltage V, undergoes even slight variation, the operating conditions P, V, T also change for the monitoring circuit 3 The logic circuit realized by the delay chain 6 of the monitoring sensor 3 is therefore subject to the actual operating conditions of the electronic circuit 2 So that the transmission time of the clock signal H is affected in the same way as in the electronic circuit 2. Therefore, the transmission time If an electronic circuit is known for each operating condition, if the measured delay differs from the value expected by the control loop 8, it means that the operating conditions are slightly different and that the logic circuit corresponding to the critical path of the electronic circuit 2 is different. For the same combination of coarse operating condition values received by the receiving module 9, there is a set of several possible reference logic circuits. The selection module 10 of the control loop 8 thus determines a set of reference logic circuits from the operating conditions delivered by the receiving module. The selection module 10 is configured to select a logic circuit from the set of reference logic circuits for the given operating conditions. If the selection module 10 receives a delay interval delivered by the comparison module 11, the selection module reduces the set of reference logic circuits from the delay interval. The measured range can be considered as a finer measure of the operating conditions. The selection module 10 is configured to select a logic circuit from the set of reference logic circuits if the restricted set comprises a plurality of reference logic circuits.

The new logic circuit selected is constructed to have the same delay as the previous logic circuit for the same operating conditions P, V, T, but is more sensitive to operating conditions than the previous one. Consequently, the measured delay may differ from the previous one, so that by comparing the new measured delay with the same thresholds, the measured delay can be in another delay interval and the selection module 10 of the control loop 8 can modify the selected logic circuit again or not. The logic circuit is thus modified as long as the measured delay differs from the preceding one by a value greater than one of the thresholds. FIG. 4 schematically represents an example of a delay chain 6 according to one embodiment of the monitoring circuit 3 of FIG. 2.

In this example, the delay chain comprises three multiplexers 12. The first multiplexer 12 is coupled to eight inverters 13 arranged at the input of the first multiplexer 12 so as to be combined according to different configuration. The second multiplexer 12 is coupled, on the one hand, to two NAND gates 14, and, on the other hand, to two NOR gates 15. The NAND gates 14 and NOR 15 are arranged at the input of the second multiplexer 12 so as to be combined according to different configuration. Finally, the third multiplexer 12 is coupled to other inverters 13 separated by long interconnection wires in order to integrate an RC type component into the delay, and arranged at the input to allow different possible combinations, a possible combination comprising an even number of inverters. The three multiplexers 12 are coupled together so as to allow the realization of a logic circuit receiving as input the clock signal H and outputting the delayed clock signal H +. The delay chain 6 further comprises a control input 16 receiving the control signal delivered by the selection module 10 of the control loop 8. The control input 16 is coupled to a processing module 17 delivering a control signal. separate control at each multiplexer 12 for producing the logic circuit selected by the selection module 10 of the control loop 8.

FIG. 5 schematically shows an example of a time-to-digital converter 7 according to an embodiment of the monitoring circuit of FIG. 2. The time-digital converter 7 makes it possible to measure the delay between the clock signal H and the signal of delayed clock H + using logic means for delivering the measured delay in the form of a thermometric code. The measured delay being expressed in the form of a thermometric code, the thresholds of the comparison module 11 of the control loop 8 are threshold thermometric codes.

The time-digital converter 7 comprises a first input 18 receiving the clock signal H and a second input receiving the delayed input signal H +. It comprises a first logic line 20 coupled to the first input 18 and a second logic line 21 coupled to the second input 19. The logic lines 20 and 21 each comprise a succession of measuring points respectively 22 and 23 between which is coupled at least a logic gate respectively 24 and 25. Each logic gate 24 of the first logic line 20 delivers a signal with a given delay with respect to each logic gate 25 of the second logic circuit 21; i.e., the processing time of a logic gate 24 of the first logic line 20 is longer than the processing time of a logic gate 25 of the second logic line 21.

Each pair of measurement points 22 and 23 is coupled to the input of a flip-flop 26 so as to perform a comparative measurement. The latches 26 are configured to output a non-zero signal as long as there is a positive delay between the clock signal H and the delayed clock signal H +.

Thus, as the clock signals H and delayed clock H + are respectively transmitted in the first and second logic lines 20 and 21, the successive flip-flops 26 display a non-zero result as long as the delay added by the cells 24 at the clock signal H during the course of the line 20 is less than the delay of the delayed clock H +, and as soon as the two signals are in the high state, the flip-flops 26 deliver a zero signal. The logic gates 24 and 25 of the first and second logic lines 20 and 21 are arranged so that at the ends of each logic line 20 and 21, there are three logic gates 24 or 25 connected in series between two measuring points 22 or 22. 23 of the same logic line 20 or 21. This arrangement can be repeated between measurement points 22 or 23 following. The arrangement of the logic gates 24 and 25 respectively on the first and second logic lines 20 and 21 is further realized so that in the center of each logic line 20 and 21, there is a single logic gate 24 or 25 connected between two measuring points 22 or 23 of the same logic line 20 or 21, each space between two measurement points around the center of the logic line may also comprise a single logic gate 24 or 25. Between the end zones comprising three logic gates 24 or 25 coupled between two measuring points 22 or 23, and the central zone comprising a single logic gate 24 or 25 coupled between two measuring points 22 or 23, spaces between two measuring points 22 or 23 may comprise two logic gates 24 or 25 coupled between two measuring points 22 or 23. The fewer logic gates between two measurement points, the smaller the time interval between two measurements, from one measurement point to another, plus the Precision of the delay measurement is great.

By varying the number of logic gates coupled between two measurement points, and thus the time interval between two measurements, the time measurement range is increased for a given number of measurement points. Each flip-flop 26 is coupled to an output module 27 capable of outputting the time-digital converter 7 with a thermometric code corresponding to the measured delay between the clock signal H and the delayed clock signal H +. The thermometric code thus obtained can be outputted to a parameterization circuit 30 of the integrated circuit 1, illustrated in FIG. 1, in order to adjust the operating parameters of the electronic circuit 2 of the integrated circuit 1 in the event of significant time drift, for example. The thermometric code is also transmitted to the control loop 8 so as to refine the set of reference logic circuits and adjust the selection of the logic circuit if necessary. FIG. 6 presents a flowchart of a method of emulation of the critical path of the electronic circuit 2 of the integrated circuit 1 according to an implementation mode.

In a first step 500, operating conditions of the electronic circuit 2 are received, then, in a step 510, a logic circuit representative of the critical path of the electronic circuit 2 is selected from among a set of reference logic circuits from the conditions of operation P, V, T of the electronic circuit 2. In a next step 520, the delay chain 6 carries out the selected logic circuit. The logic circuit is realized by combining at least a part of the logic components of a set of logic components included in the delay chain 6. Then in a following step 530, the clock signal H delivered to the electronic circuit 2 qu is input to the configurable delay chain 6 of the monitoring circuit 3 of the integrated circuit. In a subsequent step 540, the delay chain 6 delivers a delayed clock signal H + corresponding to the clock signal transmitted by the logic circuit produced by the delay chain 6. In a following step 550, the time delay between the clock signal H and the delayed clock signal H +. In a next step 560, operating conditions of the electronic circuit 2 are received again, and then, in a step 570, a logic circuit representative of the critical path of the electronic circuit 2 is selected from a set of reference logic circuits from the signal of the clock H, the delayed clock signal H + and the operating conditions P, V, T of the electronic circuit 2. In a following step 580, the delay chain 6 realizes the logic circuit selected by the selection module 10. the control loop 8. The logic circuit is realized by combining at least a part of the logical components of a set of logic components included in the delay chain 6. In the step 550 of measuring the delay, the delay is measured at using a time-to-digital converter 7 delivering a thermometric code. The delivered signal is then compared to at least one threshold code. The selection of the logic circuit in step 570 is then performed according to the operating conditions received in step 550 and the result of said comparison. Steps 530 to 580 are repeated during the monitoring of the electronic circuit. The selected logic circuit remains unchanged as long as the operating conditions are the same and the delivered temperature code is within the same delay interval.

Claims (16)

REVENDICATIONS1. Integrated circuit (1) comprising an electronic circuit (2) and a monitoring circuit (3) of said electronic circuit (2), the monitoring circuit (3) being configured to emulate a critical path of the electronic circuit (2), characterized in the monitoring circuit comprises: - a clock input (5) for receiving the clock signal (H) delivered to the electronic circuit (2), - a configurable delay chain (6) having logic components, and having a channel input connected to the clock input (5) and a channel output capable of delivering a delayed clock signal (H +), and - a control loop (8) configured to select a representative logic circuit the critical path among a set of reference logic circuits from the clock signal (H), the delayed clock signal (H +) and the operating conditions (P, V, T) of the electronic circuit (2) and to deliver a configuration signal to the ch delay timer (6) to configure said selected logic circuit. 2. Integrated circuit (1) according to claim 1, characterized in that the delay chain (6) comprises a set of logic components and arrangement means able to combine at least a part of said logic gates to produce the logic circuit selected by the control loop (8). 3. Integrated circuit (1) according to one of claims 1 or 2, wherein the monitoring circuit (3) comprises measuring means (7) for determining the time delay between the clock signal (H) and the delayed clock signal (H +), and the control loop (8) comprises a comparison module (11) able to compare the measured delay with at least one threshold, the comparison module (11) being coupled to an input a selection module (10) configured to select said logic circuit according to the operating conditions (P, V, T) and the output signal of the comparison module (11). 4. Integrated circuit (1) according to claim 3, wherein the measuring means (7) comprise a digital time converter able to measure the delay and convert the delay into a thermometric code, and the thresholds of the comparison module the loop of control (8) are threshold temperature codes. 5. Integrated circuit (1) according to claim 4, wherein the time-digital converter comprises logic means able to measure said delay with a finer precision around the value of the period of the clock signal (H) of the circuit. electronics (2) and a coarser accuracy at values further away from the period of the clock signal (H) of the electronic circuit (2). 6. Integrated circuit (1) according to one of claims 4 or 5, wherein the logic means of the time-to-digital converter comprise a first logic circuit (20) coupled to the input of the clock signal (H) and a second logic circuit (21) coupled to the input of the delayed signal (H +) from the delay chain (6), the first and second logic circuits (20, 21) each comprising logic gates (24, 25), each logic gate (24) of the first circuit (20) delivering the signal with a given delay with respect to each logic gate (25) of the second logic circuit (21). Integrated circuit (1) according to one of claims 1 to 6, wherein the delay chain (6) comprises a plurality of multiplexers (12), each multiplexer (12) comprising a plurality of logic components (13, 14). , 15) input coupled so as to offer several possible logical combinations. 8. Integrated circuit (1) according to one of claims 1 to 5, wherein the operating conditions (P, V, T) of the electronic circuit (2) comprise the voltage (V) imposed on the terminals of the electronic circuit (2). ), the temperature (T) of the electronic circuit (2), and the operating mode (P) of the transistors of the electronic circuit (2). 9. A method for emulating the critical path of an electronic circuit (2) of an integrated circuit (1), the method comprising: a) a reception (500) of the clock signal (H) delivered to the electronic circuit ( 2), b) a transmission (510) of a delayed clock signal (H +) by a configurable delay chain (6) having logic components and receiving the input clock signal (H), c) a receiving (530) the operating conditions (P, V, T) of the electronic circuit (2), d) selecting (540) a logic circuit representative of the critical path from a set of reference logic circuits from the signal clock (H), the delayed clock signal (H +) and the operating conditions (P, V, T) of the electronic circuit (2), and e) a configuration (550) of the delay chain (6). ) so as to realize the selected logic circuit. The method of claim 9, wherein the delay chain (6) realizes the selected logic circuit from a combination of at least a portion of a set of logical components. The method according to claim 9, wherein the time delay between the clock signal (H) and the delayed clock signal (H +) is measured (520), and the measured delay is compared with at least one threshold, the selection of the logic circuit being performed according to the operating conditions (P, V, T) and the result of said comparison. 12. The method of claim 10, wherein the steps a) to e) are repeated, the selected logic circuit remaining unchanged as long as the operating conditions (P, V, T) are the same and the measured delay is included in FIG. the same delay interval as the previous measured delay, a delay interval being defined by at least one of the thresholds. 13. Method according to one of claims 9 or 11, wherein said delay is measured with a finer precision around the value of the period of the clock signal (H) of the electronic circuit (2) and a coarser accuracy. at values further from the period of the clock signal (H) of the electronic circuit (2). 14. Method according to one of claims 9 to 12, wherein for measuring the delay, is regularly delayed propagation of the clock signal (H) with respect to the propagation of the delayed clock signal (H +), the line propagation (20) of the clock signal (H) comprising logic gates (24) delivering a signal with a given delay with respect to the logic gates (25) of the propagation line (21) of the delayed clock signal ( H +). The method according to one of claims 9 to 13, wherein a part of the set of logic components is combined by means of multiplexers (12), each multiplexer (12) comprising a plurality of logic gates (13, 14, 15) coupled in input so as to offer several possible combinations. 16. Method according to one of claims 9 to 14, wherein the operating conditions (P, V, T) of the electronic circuit (2) comprise the voltage (V) imposed on the terminals of the electronic circuit (2), the temperature (T) of the electronic circuit (2), and the operating mode (P) of the transistors of the electronic circuit (2).