FR3010598B1 - Procede de gestion de coherence de caches - Google Patents
Procede de gestion de coherence de cachesInfo
- Publication number
- FR3010598B1 FR3010598B1 FR1358597A FR1358597A FR3010598B1 FR 3010598 B1 FR3010598 B1 FR 3010598B1 FR 1358597 A FR1358597 A FR 1358597A FR 1358597 A FR1358597 A FR 1358597A FR 3010598 B1 FR3010598 B1 FR 3010598B1
- Authority
- FR
- France
- Prior art keywords
- coaches
- managing coherence
- coherence
- managing
- coherence coaches
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/0824—Distributed directories, e.g. linked lists of caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
- H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
- H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/30—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
- H04L9/304—Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy based on error correction codes, e.g. McEliece
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1052—Security improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/283—Plural cache memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
- G06F2212/621—Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/122—Hardware reduction or efficient architectures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/127—Trusted platform modules [TPM]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/34—Encoding or coding, e.g. Huffman coding or error correction
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Storage Device Security (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1358597A FR3010598B1 (fr) | 2013-09-06 | 2013-09-06 | Procede de gestion de coherence de caches |
CN201480053601.7A CN105580308B (zh) | 2013-09-06 | 2014-09-05 | 用于管理高速缓存一致性的方法 |
US14/916,915 US9734065B2 (en) | 2013-09-06 | 2014-09-05 | Method of managing consistency of caches |
PCT/EP2014/068990 WO2015032921A1 (fr) | 2013-09-06 | 2014-09-05 | Procédé de gestion de cohérence de caches |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1358597A FR3010598B1 (fr) | 2013-09-06 | 2013-09-06 | Procede de gestion de coherence de caches |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3010598A1 FR3010598A1 (fr) | 2015-03-13 |
FR3010598B1 true FR3010598B1 (fr) | 2017-01-13 |
Family
ID=50069025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1358597A Active FR3010598B1 (fr) | 2013-09-06 | 2013-09-06 | Procede de gestion de coherence de caches |
Country Status (4)
Country | Link |
---|---|
US (1) | US9734065B2 (fr) |
CN (1) | CN105580308B (fr) |
FR (1) | FR3010598B1 (fr) |
WO (1) | WO2015032921A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109711177A (zh) * | 2018-12-14 | 2019-05-03 | 国家电网有限公司 | 基于生物信息识别的数据安全管理方法及终端设备 |
CN111367886B (zh) * | 2020-03-02 | 2024-01-19 | 中国邮政储蓄银行股份有限公司 | 数据库中数据迁移的方法及装置 |
US12013780B2 (en) * | 2020-08-19 | 2024-06-18 | Google Llc | Multi-partition memory sharing with multiple components |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996042155A1 (fr) * | 1995-06-08 | 1996-12-27 | Motorola Inc. | Procedes de chiffrement de paquets de donnees et de detection d'erreurs de dechiffrage |
ATE522039T1 (de) | 2000-01-21 | 2011-09-15 | Sony Computer Entertainment Inc | Vorrichtung und verfahren zur verarbeitung von verschlüsselten daten |
KR100755683B1 (ko) * | 2003-05-07 | 2007-09-05 | 삼성전자주식회사 | 컨텐츠 제공자 인증 및 컨텐츠 무결성 보장 방법 |
US8296581B2 (en) * | 2007-02-05 | 2012-10-23 | Infineon Technologies Ag | Secure processor arrangement having shared memory |
US8438452B2 (en) * | 2008-12-29 | 2013-05-07 | Intel Corporation | Poison bit error checking code scheme |
US8732396B2 (en) * | 2009-06-08 | 2014-05-20 | Lsi Corporation | Method and apparatus for protecting the integrity of cached data in a direct-attached storage (DAS) system |
US20110197031A1 (en) * | 2010-02-05 | 2011-08-11 | Nokia Corporation | Update Handler For Multi-Channel Cache |
CN101958834B (zh) * | 2010-09-27 | 2012-09-05 | 清华大学 | 支持高速缓存一致的片上网络系统及数据请求方法 |
US8930647B1 (en) * | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9311250B2 (en) * | 2011-12-19 | 2016-04-12 | Intel Corporation | Techniques for memory de-duplication in a virtual system |
-
2013
- 2013-09-06 FR FR1358597A patent/FR3010598B1/fr active Active
-
2014
- 2014-09-05 WO PCT/EP2014/068990 patent/WO2015032921A1/fr active Application Filing
- 2014-09-05 CN CN201480053601.7A patent/CN105580308B/zh active Active
- 2014-09-05 US US14/916,915 patent/US9734065B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
FR3010598A1 (fr) | 2015-03-13 |
CN105580308B (zh) | 2018-12-28 |
WO2015032921A1 (fr) | 2015-03-12 |
US20160224469A1 (en) | 2016-08-04 |
CN105580308A (zh) | 2016-05-11 |
US9734065B2 (en) | 2017-08-15 |
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Legal Events
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Owner name: SAFRAN ELECTRONICS & DEFENSE, FR Effective date: 20161223 |
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