FR2987527B1 - Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees - Google Patents

Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees

Info

Publication number
FR2987527B1
FR2987527B1 FR1251688A FR1251688A FR2987527B1 FR 2987527 B1 FR2987527 B1 FR 2987527B1 FR 1251688 A FR1251688 A FR 1251688A FR 1251688 A FR1251688 A FR 1251688A FR 2987527 B1 FR2987527 B1 FR 2987527B1
Authority
FR
France
Prior art keywords
memory banks
interconnection network
control unit
processing elements
data frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1251688A
Other languages
English (en)
Other versions
FR2987527A1 (fr
Inventor
Philippe Coussy
Cyrille Chavet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Universite de Bretagne Sud
Original Assignee
Centre National de la Recherche Scientifique CNRS
Universite de Bretagne Sud
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS, Universite de Bretagne Sud filed Critical Centre National de la Recherche Scientifique CNRS
Priority to FR1251688A priority Critical patent/FR2987527B1/fr
Priority to PCT/EP2013/053613 priority patent/WO2013124449A1/fr
Priority to US14/380,554 priority patent/US9971684B2/en
Priority to EP13711578.8A priority patent/EP2817886A1/fr
Publication of FR2987527A1 publication Critical patent/FR2987527A1/fr
Application granted granted Critical
Publication of FR2987527B1 publication Critical patent/FR2987527B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H03M13/2775—Contention or collision free turbo code internal interleaver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2789—Interleaver providing variable interleaving, e.g. variable block sizes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6513—Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6519—Support of multiple transmission or communication standards
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/251—Local memory within processor subsystem
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

L'invention concerne un dispositif d'entrelacement/désentrelacement de données numériques délivrées par des éléments de traitement (P ... P ). Il comprend des bancs mémoires (B ...B ) pour stocker des données en provenance ou à destination des éléments de traitement, un réseau d'interconnexion (INT) pour aiguiller les données entre les éléments de traitement et les bancs mémoires, et une unité de contrôle (CTRL) pour commander le réseau d'interconnexion et les bancs mémoires. Selon l'invention, l'unité de contrôle (CTRL) comprend un circuit de calcul (CAL) apte à générer en ligne des mots de commande du réseau d'interconnexion et des séquences d'adressage et de contrôle des bancs mémoires garantissant un accès mémoire sans conflit en fonction de la règle d'entrelacement à appliquer, de la taille des trames de données numériques, du nombre d'unités de traitement et de bancs mémoires et du réseau d'interconnexion. On peut ainsi réduire drastiquement le nombre de mémoires dans l'unité de contrôle.
FR1251688A 2012-02-23 2012-02-23 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees Expired - Fee Related FR2987527B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1251688A FR2987527B1 (fr) 2012-02-23 2012-02-23 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees
PCT/EP2013/053613 WO2013124449A1 (fr) 2012-02-23 2013-02-22 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees
US14/380,554 US9971684B2 (en) 2012-02-23 2013-02-22 Self-configurable device for interleaving/deinterleaving data frames
EP13711578.8A EP2817886A1 (fr) 2012-02-23 2013-02-22 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1251688A FR2987527B1 (fr) 2012-02-23 2012-02-23 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees

Publications (2)

Publication Number Publication Date
FR2987527A1 FR2987527A1 (fr) 2013-08-30
FR2987527B1 true FR2987527B1 (fr) 2014-02-21

Family

ID=47988889

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1251688A Expired - Fee Related FR2987527B1 (fr) 2012-02-23 2012-02-23 Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees

Country Status (4)

Country Link
US (1) US9971684B2 (fr)
EP (1) EP2817886A1 (fr)
FR (1) FR2987527B1 (fr)
WO (1) WO2013124449A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9454313B2 (en) 2014-06-10 2016-09-27 Arm Limited Dynamic selection of memory management algorithm
US9875195B2 (en) 2014-08-14 2018-01-23 Advanced Micro Devices, Inc. Data distribution among multiple managed memories
EP4358416A3 (fr) 2018-11-07 2024-05-08 Telefonaktiebolaget LM Ericsson (publ) Mise en uvre optimisée d'entrelacement (dés) pour une nouvelle radio 3gpp

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2675970B1 (fr) 1991-04-23 1993-08-06 France Telecom Procede de codage convolutif correcteur d'erreurs pseudo-systematique, procede de decodage et dispositifs correspondants.
FR2838581B1 (fr) 2002-04-16 2005-07-08 Universit De Bretagne Sud Procede de codage et/ou de decodage de codes correcteurs d'erreurs, dispositifs et signal correspondants
US7454570B2 (en) * 2004-12-07 2008-11-18 International Business Machines Corporation Efficient memory update process for on-the-fly instruction translation for well behaved applications executing on a weakly-ordered processor
WO2006082923A1 (fr) 2005-02-03 2006-08-10 Matsushita Electric Industrial Co., Ltd. Entrelaceur parallele, desentrelaceur parallele et procede d'entrelacement
FR2915641B1 (fr) * 2007-04-30 2009-08-07 St Microelectronics Sa Procede et dispositif d'entrelacement de donnees
EP2210345A2 (fr) * 2007-10-02 2010-07-28 Imec Architecture asip (processeur d'ensembles d'instructions spécifique à une application) permettant de décoder au moins deux procédés de décodage
FR2931968B1 (fr) * 2008-06-02 2012-11-30 Alcatel Lucent Procede et equipement de stockage de donnees en ligne
TWI381653B (zh) * 2009-09-11 2013-01-01 Ind Tech Res Inst 二階重排多項式交織器位址產生裝置與方法

Also Published As

Publication number Publication date
WO2013124449A1 (fr) 2013-08-29
US9971684B2 (en) 2018-05-15
FR2987527A1 (fr) 2013-08-30
US20150301940A1 (en) 2015-10-22
EP2817886A1 (fr) 2014-12-31

Similar Documents

Publication Publication Date Title
TWI635349B (zh) 藉由組合攝影機及攝影機圖符功能性最大化行動裝置之顯示區的設備與方法
JP2007529951A5 (fr)
FR2987527B1 (fr) Dispositif auto-configurable d'entrelacement/desentrelacement de trames de donnees
SE0502492L (sv) Kontantdepineringsanordning och associerade förfaranden och anordningar
CN106294603A (zh) 文件存储方法及装置
US20160266607A1 (en) System for integrating commercial off-the-shelf devices to produce a modular interaction platform
US11122002B2 (en) Storing messages of a message queue
US9792251B2 (en) Array of processor core circuits with reversible tiers
US10318133B2 (en) Display control of an image on a display screen
US9697208B2 (en) Identifying content under access control
WO2008038204A3 (fr) traitement de données avec une pluralité de bancs de mémoire
JP2017537371A5 (fr)
US10878608B2 (en) Identifying planes in artificial reality systems
WO2017129911A3 (fr) Assistant numérique personnel emboitant un ordiphone, un clavier et une tablette capable de prendre des images
FR2924104B1 (fr) Systeme de repartition de barres de produits alimentaires
US9204047B2 (en) Imaging
JP2013020395A5 (fr)
CN108549716A (zh) 一种基于布隆算法实现海量黑名单处理的方法
US10579428B2 (en) Data token management in distributed arbitration systems
WO2016034421A3 (fr) Dispositif et procédé pour améliorer l'efficacité de rendu d'image
MY177317A (en) An electronic platform
US20160070484A1 (en) Data shuffling in a non-uniform memory access device
CN108846808B (zh) 一种图像处理的方法及其装置
US10114202B2 (en) Dual purpose microscope
CN101859280A (zh) 一种二维图像数据的并行传输计算方法及系统

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 9

ST Notification of lapse

Effective date: 20211005