FR2984596A1 - Extended drain P-channel metal-oxide-semiconductor transistor manufacturing method for voltage regulation device of mobile phone, involves forming drain contact area in P-type housing remote from P-type housing/N-type body housing junction - Google Patents

Extended drain P-channel metal-oxide-semiconductor transistor manufacturing method for voltage regulation device of mobile phone, involves forming drain contact area in P-type housing remote from P-type housing/N-type body housing junction Download PDF

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Publication number
FR2984596A1
FR2984596A1 FR1161807A FR1161807A FR2984596A1 FR 2984596 A1 FR2984596 A1 FR 2984596A1 FR 1161807 A FR1161807 A FR 1161807A FR 1161807 A FR1161807 A FR 1161807A FR 2984596 A1 FR2984596 A1 FR 2984596A1
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type
drain
well
gate
transistors
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French (fr)
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Dominique Golanski
Raul Andres Bianchi
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Abstract

The method involves forming a P-type housing (23) juxtaposed with an N-type body housing (25) of an extended drain P-channel metal-oxide-semiconductor (MOS) transistor, where the P-type housing is formed during formation of P-type body housings of N-channel transistors. A drain contact area (37) is formed in the P-type housing remote from a junction between the P-type housing and the N-type body housing. An independent claim is also included for an extended drain P-channel MOS transistor.

Description

B11376 - 11-GR3-0737FR01 1 PROCÉDÉ DE FABRICATION D'UN TRANSISTOR MOS À CANAL P À DRAIN ÉTENDU Domaine de l'invention La présente invention concerne un procédé de fabrication d'un transistor MOS à canal P à drain étendu dans une filière technologique CMOS, c'est-à-dire dans une filière adaptée à la fabrication de transistors MOS à canal N et de transistors MOS à canal P dans un même substrat semiconducteur. Exposé de l'art antérieur Dans certains appareils électroniques, comme par exemple des téléphones portables, on est parfois amené à prévoir des dispositifs de régulation de la tension d'alimentation de divers composants de ces appareils. Ces tensions d'alimentation sont par exemple de l'ordre de 5 V. Les dispositifs de régulation de tension comprennent généralement des transistors MOS, et sont intégrés soit dans des puces spécifiquement dédiées aux fonctions de régulation de tension, soit dans des puces réalisant également d'autres fonctions de l'appareil. Les puces réalisant des fonctions autres que les fonctions de régulation de tension sont généralement fabriquées dans des technologies CMOS dans lesquelles les transistors ne peuvent supporter que des tensions d'alimentation nettement inférieures aux tensions d'alimentation des autres composants de B11376 - 11-GR3-0737FR01 2 l'appareil électronique. A titre d'exemple, la tension d'alimentation des transistors MOS est de l'ordre de 1,1 V pour des transistors dont la dimension minimale (longueur de grille) est inférieure à 65 nm. TECHNICAL FIELD The present invention relates to a method of manufacturing an extended drain P-channel MOS transistor in a technological sector. CMOS, that is to say in a sector adapted to the manufacture of N-channel MOS transistors and P-channel MOS transistors in the same semiconductor substrate. DISCUSSION OF THE PRIOR ART In certain electronic devices, such as for example mobile telephones, it is sometimes necessary to provide devices for regulating the supply voltage of various components of these devices. These supply voltages are for example of the order of 5 V. Voltage regulation devices generally comprise MOS transistors, and are integrated either in chips specifically dedicated to voltage regulation functions, or in chips also realizing other functions of the device. Chips performing functions other than voltage regulation functions are generally manufactured in CMOS technologies in which the transistors can only withstand supply voltages well below the supply voltages of the other components of the B11376 - 11-GR3- 0737EN01 2 the electronic device. By way of example, the supply voltage of the MOS transistors is of the order of 1.1 V for transistors whose minimum dimension (gate length) is less than 65 nm.

Pour supporter une tension plus élevée que celle que supportent des transistors MOS classiques, on a proposé d'utiliser des transistors MOS à drain étendu. Dans de tels transistors, le drain comporte une région de contact de drain séparée du bord de la région de canal par une zone d'extension de drain du même type de conductivité que la région de contact de drain mais moins fortement dopée. Un inconvénient des transistors MOS à drain étendu connus réside dans le fait que la formation de la zone d'extension de drain requiert au moins une étape d'implantation spécifique supplémentaire par rapport aux étapes de fabrication des transistors MOS classiques de la filière technologique considérée. Il en résulte une augmentation du coût de fabrication. En outre, lorsque le drain d'un transistor MOS à drain étendu connu est polarisé à une tension qui est par exemple de l'ordre de 5 V, le fort champ électrique présent dans la région du canal la plus proche du drain est responsable de l'injection de porteurs chauds dans l'isolant de grille. Ces porteurs chauds entraînent des dégradations et réduisent la durée de vie du transistor. Un autre inconvénient des transistors MOS à drain étendu connus réside dans l'augmentation de la résistance à l'état passant du transistor MOS due à l'augmentation de la résistance d'accès au drain. Pour pallier cet inconvénient, on prévoit généralement une augmentation de la largeur du transistor et donc de sa surface, ce qui n'est pas souhaitable. Dans des transistors à drain étendu connus, il existe un compromis difficile à satisfaire pour optimiser la durée de vie, la résistance à l'état passant et la surface des 35 transistors. To support a voltage higher than that supported by conventional MOS transistors, it has been proposed to use extended drain MOS transistors. In such transistors, the drain has a drain contact region separated from the edge of the channel region by a drain extension zone of the same conductivity type as the drain contact region but less heavily doped. A disadvantage of known extended-drain MOS transistors lies in the fact that the formation of the drain extension zone requires at least one additional specific implantation step with respect to the manufacturing steps of the conventional MOS transistors of the technological sector under consideration. This results in an increase in the manufacturing cost. In addition, when the drain of a known extended drain MOS transistor is biased at a voltage which is for example of the order of 5 V, the strong electric field present in the region of the channel closest to the drain is responsible for the injection of hot carriers into the gate insulator. These hot carriers cause damage and reduce the life of the transistor. Another disadvantage of known extended-drain MOS transistors lies in the increase of the on-state resistance of the MOS transistor due to the increase of the resistance of access to the drain. To overcome this drawback, there is generally an increase in the width of the transistor and therefore its surface, which is not desirable. In known extended-drain transistors, there is a compromise difficult to satisfy in order to optimize the lifetime, the on-state resistance and the surface of the transistors.

B11376 - 11-GR3-0737FR01 3 Résumé Ainsi, un objet d'un mode de réalisation de la présente invention est de prévoir un procédé de fabrication d'un transistor MOS à drain étendu palliant au moins en partie 5 certains des inconvénients des procédés connus. Un objet d'un mode de réalisation de la présente invention est de prévoir un procédé de fabrication d'un transistor MOS à drain étendu ne nécessitant pas d'étape de fabrication supplémentaire par rapport aux étapes utilisées pour 10 la fabrication de transistors MOS classiques, c'est-à-dire sans extension de drain, dans des technologies CMOS. Un autre objet d'un mode de réalisation de la présente invention est de prévoir un transistor MOS à drain étendu présentant une résistance à l'état passant réduite par rapport 15 aux transistors MOS à drain étendu connus. Un autre objet d'un mode de réalisation de la présente invention est de prévoir un transistor MOS à drain étendu présentant une durée de vie améliorée par rapport aux transistors MOS à drain étendu connus. 20 Ainsi, un mode de réalisation de la présente invention prévoit un procédé de fabrication d'un transistor MOS à canal P à drain étendu, dans une filière technologique adaptée à la fabrication de transistors MOS à canal N et de transistors MOS à canal P dans un substrat semiconducteur, ce procédé utilisant 25 essentiellement les étapes de fabrication de transistors à canal P avec les modifications suivantes : former un premier caisson de type P juxtaposé à un second caisson de corps de type N du transistor à drain étendu, le premier caisson étant formé en même temps que des caissons de corps de type P de transistors à 30 canal N ; et former une région de contact de drain dans le premier caisson à distance de la jonction entre les premier et second caissons. Selon un mode de réalisation de la présente invention, le procédé comprend en outre une étape de formation d'une grille B11376 - 11-GR3-0737FR01 4 s'étendant au-dessus d'une partie du second caisson et d'une partie du premier caisson. Selon un mode de réalisation de la présente invention, la région de contact de drain du transistor à drain étendu est 5 formée à distance de la grille. Selon un mode de réalisation de la présente invention, le procédé comprend en outre une étape de dépôt d'une couche d'un matériau isolant au-dessus du substrat, entre la grille et la région de contact de drain, cette étape précédant une étape 10 de siliciuration. Selon un mode de réalisation de la présente invention, ladite filière est adaptée à la fabrication de transistors MOS d'une première épaisseur de grille et de transistors MOS d'une seconde épaisseur de grille inférieure à la première épaisseur. 15 Selon un mode de réalisation de la présente invention, le procédé comprend en outre une étape de formation d'une région de source dans le second caisson, la région de source comportant une portion moins fortement dopée à proximité de la grille, et une étape de formation d'une poche de type N, plus fortement 20 dopée que le second caisson, s'étendant autour de la région de source et de la portion moins fortement dopée, la portion moins fortement dopée et la poche de type N étant formées en même temps que des portions moins fortement dopées et des poches de type N dans des régions de source et de drain de transistors à 25 canal P de la seconde épaisseur. Selon un mode de réalisation de la présente invention, le procédé comprend en outre une étape de formation d'une couche enterrée de type N au-dessous du premier caisson. Un mode de réalisation de la présente invention 30 prévoit en outre un transistor MOS à canal P à drain étendu, comprenant : un premier caisson de type P juxtaposé à un second caisson de corps de type N ; et une région de contact de drain s'étendant dans le premier caisson à distance de la jonction entre le premier et le second caisson. B11376 - 11-GR3-0737EN01 3 Summary Thus, an object of an embodiment of the present invention is to provide a method of manufacturing an extended drain MOS transistor at least partially overcoming some of the disadvantages of known methods. . An object of an embodiment of the present invention is to provide a method for manufacturing an extended drain MOS transistor that does not require an additional manufacturing step with respect to the steps used for manufacturing conventional MOS transistors, that is, without drain extension, in CMOS technologies. Another object of an embodiment of the present invention is to provide an extended drain MOS transistor having reduced on-state resistance with respect to known extended drain MOS transistors. Another object of an embodiment of the present invention is to provide an extended drain MOS transistor having an improved lifetime compared to known extended drain MOS transistors. Thus, an embodiment of the present invention provides a method of manufacturing an extended drain P-channel MOS transistor in a technological pathway suitable for manufacturing N-channel MOS transistors and P-channel MOS transistors in a semiconductor substrate, which method essentially uses the steps of manufacturing P-channel transistors with the following modifications: forming a first P-type well juxtaposed with a second N-type body well of the extended drain transistor, the first well being formed at the same time as P-type body wells of N-channel transistors; and forming a drain contact region in the first well away from the junction between the first and second wells. According to an embodiment of the present invention, the method further comprises a step of forming a gate extending over a portion of the second caisson and a portion of the cathode. first box. According to one embodiment of the present invention, the drain contact region of the extended drain transistor is formed away from the gate. According to an embodiment of the present invention, the method further comprises a step of depositing a layer of an insulating material on top of the substrate, between the gate and the drain contact region, this step preceding a step Silicidation. According to an embodiment of the present invention, said die is suitable for manufacturing MOS transistors with a first gate thickness and MOS transistors with a second gate thickness smaller than the first thickness. According to an embodiment of the present invention, the method further comprises a step of forming a source region in the second well, the source region having a less heavily doped portion near the gate, and a step forming an N-type pocket, more heavily doped than the second well, extending around the source region and the less heavily doped portion, the less heavily doped portion and the N-type pocket being formed into same time as less heavily doped portions and N-type pockets in source and drain regions of P-channel transistors of the second thickness. According to one embodiment of the present invention, the method further comprises a step of forming a buried N-type layer below the first box. An embodiment of the present invention further provides an extended drain P-channel MOS transistor, comprising: a first P-type well juxtaposed with a second N-type body well; and a drain contact region extending into the first well away from the junction between the first and second wells.

B11376 - 11-GR3-0737FR01 Selon un mode de réalisation de la présente invention, le transistor MOS comprend en outre une grille s'étendant au-dessus d'une partie du second caisson et d'une partie du premier caisson. 5 Selon un mode de réalisation de la présente invention, la région de contact de drain est formée à distance de la grille. Un mode de réalisation de la présente invention prévoit en outre un dispositif de régulation de tension 10 comportant un transistor MOS à canal P à drain étendu tel que celui décrit ci-dessus. Brève description des dessins Ces objets, caractéristiques et avantages, ainsi que d'autres seront exposés en détail dans la description suivante 15 de modes de réalisation particuliers faite à titre non limitatif en relation avec les figures jointes parmi lesquelles : la figure 1 est une vue en coupe représentant de façon schématique divers types de transistors MOS d'une filière technologique CMOS ; et 20 les figures 2A à 2D sont des vues en coupe représentant de façon schématique des étapes successives de fabrication d'un transistor MOS à canal P à drain étendu. Par souci de clarté, de mêmes éléments ont été désignés par de mêmes références dans les différentes figures 25 et, de plus, comme cela est habituel dans la représentation des circuits intégrés, les diverses figures ne sont pas tracées à l'échelle. Description détaillée Dans des filières technologiques CMOS, deux types de 30 transistors MOS sont couramment fabriqués dans une même puce de circuit intégré : des transistors MOS présentant un isolant de grille relativement épais, et des transistors MOS présentant un isolant de grille plus mince. La figure 1 est une vue en coupe représentant de façon 35 schématique ces deux types de transistors MOS, pour des B11376 - 11-GR3-0737FR01 6 transistors à canal N et à canal P. Les divers transistors sont formés dans un même substrat semiconducteur 1 faiblement dopé de type P. Dans la partie droite de la figure 1 sont représentés 5 un transistor MOS à canal N à isolant de grille épais (NMOSGO2) et un transistor MOS à canal P à isolant de grille épais (PMOSGO2). Le transistor à canal N est formé dans un caisson de type P 3 (PwellGO2), de niveau de dopage supérieur à celui du substrat 1, tandis que le transistor à canal P est formé dans un 10 caisson de type N 5 (NwellGO2). Une couche enterrée de type N 7 (DNwellG02), est généralement formée sous le caisson PwellGO2 des transistors à canal N pour isoler le caisson du substrat. Pour la même raison, les caissons PwellGO2 sont généralement complètement entourés par des caissons de type N. 15 Le transistor NMOSGO2 comprend des régions de source et de drain 15 fortement dopées de type N, situées de part et d'autre d'une grille 11 isolée du substrat par un isolant de grille 9 d'épaisseur e2. Des espaceurs 13 s'étendent de part et d'autre de la grille 11. Les régions de source et de drain 20 peuvent comprendre en outre des portions de type N moins fortement dopées 16 à proximité de la grille 11. Les portions 16 s'étendent dans la partie supérieure du caisson sous les espaceurs 13. Pour le transistor PMOSGO2, les régions de source et de drain 15 sont fortement dopées de type P, et peuvent 25 comprendre en outre des portions 17 de type P moins fortement dopées. Dans la partie gauche de la figure 1 sont représentés un transistor MOS à canal N à isolant de grille mince (NMOSG01) et un transistor MOS à canal P à isolant de grille mince 30 (PMOSGO1). Le transistor NMOSGO1 est formé dans un caisson 4 PwellGOl de niveau de dopage généralement différent de celui du caisson 3 PwellGO2 du transistor NMOSGO2. Le transistor PMOSGO1 est formé dans un caisson 6 NwellGOl de niveau de dopage généralement différent de celui du caisson 5 NwellGO2 du 35 transistor PMOSGO2. Une couche enterrée de type N 8 (DNwellG01) B11376 - 11-GR3-0737FR01 7 s'étend généralement sous le caisson 4 de type P, et le caisson 4 est généralement complètement entouré de caissons de type N. Les transistors NMOSGO1 et PMOSGO1 comprennent une grille 11 isolée par un isolant de grille 10 d'épaisseur effective el inférieure à l'épaisseur effective e2, et des espaceurs 13 entourant la grille. Le transistor NMOSGO1 comprend des régions de source et de drain 15 fortement dopées de type N situées de part et d'autre de la grille 11. Les régions de source et de drain peuvent comprendre en outre des portions de type N moins fortement dopées 18 à proximité de la grille 11, s'étendant sous les espaceurs 13. Le transistor NMOSGO1 peut comprendre en outre des poches 19 de type P, plus fortement dopées que le caisson PwellGOl, s'étendant autour des régions de source et de drain 15 et des portions 18. Le transistor PMOSGO1 comprend des régions de source et de drain 15 fortement dopées de type P, pouvant comprendre des portions 20 de type P moins fortement dopées, et des poches 21 de type N, plus fortement dopées que le caisson NwellGOl. According to one embodiment of the present invention, the MOS transistor further comprises a gate extending over a portion of the second caisson and a portion of the first caisson. B11376 - 11-GR3-0737EN01 According to one embodiment of the present invention, the drain contact region is formed away from the gate. An embodiment of the present invention further provides a voltage regulator device 10 having an extended drain P-channel MOS transistor as described above. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying drawings in which: FIG. in section schematically representing various types of MOS transistors of a CMOS technology sector; and FIGS. 2A-2D are sectional views schematically illustrating successive steps of manufacturing an extended drain P-channel MOS transistor. For the sake of clarity, the same elements have been designated by the same references in the various figures 25 and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale. DETAILED DESCRIPTION In CMOS technology dies, two types of MOS transistors are commonly manufactured in the same integrated circuit chip: MOS transistors having a relatively thick gate insulator, and MOS transistors having a thinner gate insulator. FIG. 1 is a sectional view schematically showing these two types of MOS transistors for N-channel and P-channel transistors. The various transistors are formed in the same semiconductor substrate 1 The right-hand portion of FIG. 1 shows a thick gate insulator N-channel MOS transistor (NMOSGO2) and a thick gate insulator P-channel MOS transistor (PMOSGO2). The N-channel transistor is formed in a P-type well 3 (PwellGO2), with a doping level higher than that of the substrate 1, while the P-channel transistor is formed in an N-type well 5 (NwellGO2). An N-type buried layer 7 (DNwellG02) is generally formed under the PwellGO2 well of the N-channel transistors to isolate the subwoofer from the substrate. For the same reason, the PwellGO2 wells are generally completely surrounded by N-type wells. The NMOSGO2 transistor includes heavily N-type doped source and drain regions 15 located on either side of a gate 11. isolated from the substrate by a grid insulator 9 of thickness e2. Spacers 13 extend on either side of the gate 11. The source and drain regions 20 may furthermore comprise less heavily doped N-type portions 16 near the gate 11. extend for the PMOSGO2 transistor, the source and drain regions 15 are strongly P-type doped, and may further comprise P-less low-doped portions 17. In the left-hand part of FIG. 1, there is shown a thin gate insulator N-channel MOS transistor (NMOSG01) and a thin gate insulator P-channel MOS transistor (PMOSGO1). The NMOSGO1 transistor is formed in a PwellGOl box 4 of doping level generally different from that of the PwellGO2 box 3 of the NMOSGO2 transistor. The PMOSGO1 transistor is formed in a doping level box NwellGO1 which is generally different from that of the NwellGO2 box of the PMOSGO2 transistor. An underground layer N 8 (DNwellG01) B11376 - 11-GR3-0737EN01 7 generally extends beneath the P-type well 4, and the well 4 is generally completely surrounded by N-type wells. The NMOSGO1 and PMOSGO1 transistors comprise a gate 11 insulated by a gate insulator 10 of effective thickness and less than the effective thickness e2, and spacers 13 surrounding the gate. The NMOSGO1 transistor comprises strongly N-type doped source and drain regions located on either side of the gate 11. The source and drain regions may further comprise N-type portions that are less heavily doped 18. the NMOSGO1 transistor may further comprise P-type pockets 19, which are more heavily doped than the PwellGO1 well, extending around the source and drain regions 15 and Portions 18. The PMOSGO1 transistor includes strongly P-type source and drain regions 15, which may comprise P-type portions that are less heavily doped, and N-type pockets 21, which are more heavily doped than the NwellGO 1 well.

Les inventeurs proposent un procédé de fabrication permettant de former, dans un même substrat, des transistors MOS à canal P à drain étendu, en même temps que des transistors MOS classiques (c'est-à-dire sans extension de drain) du type décrit en relation avec la figure 1. The inventors propose a manufacturing method making it possible to form, in the same substrate, P-channel MOS transistors with extended drain, together with conventional MOS transistors (ie without drain extension) of the type described. in relation with Figure 1.

Les figures 2A à 2D sont des vues en coupe représentant de façon schématique des étapes successives d'un tel procédé de fabrication d'un transistor MOS à canal P à drain étendu. La figure 2A représente un substrat semiconducteur 1, faiblement dopé de type P, dans lequel a été formée une couche enterrée 27 de type N, cette couche étant formée en même temps que la couche 7 de la figure 1 (DNwellG02). Un caisson de type P PwellGO2 23 et un caisson de type N NwellGO2 25 ont été formés dans la partie supérieure du substrat, les caissons 23 et 25 étant juxtaposés. Les caissons 23 et 25 s'étendent à partir de B11376 - 11-GR3-0737FR01 8 la surface supérieure du substrat jusqu'à la couche enterrée 27 de type N. La profondeur des caissons est par exemple comprise entre 1,5 et 2 gm. Le niveau de dopage du caisson 23 de type P est par exemple compris entre 1017 et 1018 atomes/cm3, et celui du caisson 25 de type N est par exemple compris entre 1017 et 1018 atomes/cm3. Le caisson 23 de type P est formé en même temps que les caissons de type P PwellGO2 des transistors NMOSG02, et le caisson 25 de type N est formé en même temps que les caissons de type N NwellGO2 des transistors PMOSGO2. Alternativement, le caisson 23 de type P peut être formé en même temps que les caissons de type P PwellGOl des transistors NMOSGO1. Dans cet exemple, la couche 27 s'étend sous toute la surface inférieure du caisson 23 et sous une partie de la surface inférieure du caisson 25. Les faces du caisson 23 qui ne sont pas en contact avec le caisson 25 sont isolées du substrat 1 par un caisson de type N 26. Le caisson 26 est par exemple formé en même temps que les caissons NwellGO2 des transistors PMOSGO2 ou en même temps que les caissons NwellGOl des transistors PMOSGO1. Dans cet exemple, des tranchées isolantes peu profondes 30, par exemple remplies d'oxyde de silicium, couramment désignées dans la technique par l'acronyme STI ("Shallow Trench Isolation" - tranchée d'isolement peu profonde), ont été formées dans la partie supérieure du substrat, et sont destinées à assurer les isolements nécessaires. FIGS. 2A to 2D are sectional views schematically showing successive steps of such a method for manufacturing an extended drain P-channel MOS transistor. FIG. 2A shows a P-type lightly doped semiconductor substrate 1, in which a buried N-type layer 27 has been formed, this layer being formed at the same time as the layer 7 of FIG. 1 (DNwellG02). A PwellGO2 P type box 23 and NwellGO2 N type box 25 were formed in the upper part of the substrate, the boxes 23 and 25 being juxtaposed. The boxes 23 and 25 extend from the upper surface of the substrate to the buried layer 27 of type N. The depth of the boxes is for example between 1.5 and 2 gm. . The doping level of the P type box 23 is for example between 1017 and 1018 atoms / cm3, and that of the N type box 25 is for example between 1017 and 1018 atoms / cm3. The P-type well 23 is formed at the same time as the PwellGO2 wells of the NMOSG02 transistors, and the N-shaped well 25 is formed at the same time as the NwellGO2 N-wells of the PMOSGO2 transistors. Alternatively, the P-type box 23 may be formed at the same time as the PwellGO1 P-type boxes of the NMOSGO1 transistors. In this example, the layer 27 extends under the entire lower surface of the box 23 and under a portion of the lower surface of the box 25. The faces of the box 23 which are not in contact with the box 25 are isolated from the substrate 1 by an N-type casing 26. The casing 26 is for example formed at the same time as the NwellGO2 boxes of the PMOSGO2 transistors or at the same time as the NwellGO1 boxes of the PMOSGO1 transistors. In this example, shallow insulating trenches 30, for example filled with silicon oxide, commonly referred to in the art by the acronym STI ("Shallow Trench Isolation"), were formed in the upper part of the substrate, and are intended to provide the necessary isolations.

La figure 2B illustre une étape de formation d'une grille 31 au-dessus de la surface supérieure du substrat, isolée du substrat par un isolant de grille 29, d'épaisseur e2 dans cet exemple. La grille 31 est par exemple en silicium polycristallin. La grille 31 s'étend principalement au-dessus du caisson 25 de type N, mais s'étend aussi au-delà de la jonction entre le caisson 25 de type N et le caisson 23 de type P du côté du caisson 23 de type P. Ainsi, la jonction P-N entre les caissons 23 et 25 se trouve sous la grille 31, et ne coïncide avec aucun des bords de la grille. FIG. 2B illustrates a step of forming a gate 31 above the upper surface of the substrate, isolated from the substrate by a gate insulator 29, of thickness e2 in this example. The gate 31 is for example polycrystalline silicon. The gate 31 extends mainly above the N-type well 25, but also extends beyond the junction between the N-type well 25 and the P-type well 23 on the P-type 23 side. Thus, the PN junction between the boxes 23 and 25 is located under the grid 31, and does not coincide with any of the edges of the grid.

B11376 - 11-GR3-0737FR01 9 La figure 2C illustre une étape de formation des régions de source 35 et de contact de drain 37 du transistor à drain étendu. Préalablement à la formation des régions de source et de contact de drain, des régions de contact 33 fortement dopées de type N peuvent être formées à la surface des caissons 25 et 26 de type N pour assurer la polarisation des caissons 25, 26 et de la couche enterrée 27 de type N. Pendant l'implantation des régions de source et de contact de drain, les régions dans lesquelles on ne veut pas implanter d'élément dopant de type P sont recouvertes d'une couche de protection, par exemple en résine, 34. La région de source 35, fortement dopée de type P, est formée dans le caisson 25 de type N, tandis que la région de contact de drain 37, fortement dopée de type P, est formée dans le caisson 23 de type P. La région de contact de drain 37 est formée à distance de la jonction P-N entre le caisson 23 et le caisson 25, et, dans l'exemple représenté, à distance du bord de la grille 31 situé au-dessus du caisson 23 (côté drain). Le niveau de dopage des régions de source 35 et de contact de drain 37 est par exemple compris entre 1020 et 1021 atomes/cm3. FIG. 2C illustrates a step of forming the source 35 and drain contact 37 regions of the extended drain transistor. B11376 - 11-GR3-0737EN01 Prior to the formation of the source and drain contact regions, N-type strongly doped contact regions 33 may be formed on the surface of the N-type wells 25 and 26 to provide for the polarization of the wells 25, 26 and the N type buried layer 27. During the implantation of the source and drain contact regions, the regions in which no P-type doping element is to be implanted are covered with a protective layer, for example made of resin , 34. The P-type heavily doped source region 35 is formed in the N-type well 25, while the P-type heavily doped drain contact region 37 is formed in the P-type well 23 The drain contact region 37 is formed at a distance from the PN junction between the caisson 23 and the caisson 25, and, in the example shown, at a distance from the edge of the gate 31 situated above the caisson 23 (side drain). The doping level of the source and drain contact regions 37 is, for example, between 1020 and 1021 atoms / cm3.

Pendant l'étape de formation des régions de source 35 et de contact de drain 37, des éléments dopants de type P sont aussi implantés dans la grille 31. Afin de garantir que des éléments dopants de type P ne soient pas implantés dans le caisson 23 entre le bord de la grille et la région de contact de drain 37, la résine 34 a été formée de sorte qu'elle déborde sur le bord de la grille 31 du côté du drain. Il en résulte, comme cela apparaît sur la figure 2C, qu'une portion 32 de la grille 31 (vers le bord de la grille, côté drain) n'est pas dopée. Les régions de source et de contact de drain du transistor à drain étendu sont formées en même temps que les régions de source et de drain des transistors PMOSGO2. Le caisson 25 de type N constitue le caisson de corps du transistor à canal P à drain étendu, dans la partie supérieure duquel se forme le canal du transistor. Le canal s'étend sous la grille du bord de la région de source 35 jusqu'à la jonction entre le caisson 25 et le B11376 - 11-GR3-0737FR01 10 caisson 23. Le caisson 23 constitue la zone d'extension de drain du transistor à drain étendu. La figure 2D illustre une étape de dépôt d'une couche d'un matériau isolant 39, par exemple en oxyde de silicium, au- dessus de la zone d'extension de drain, c'est-à-dire à la surface supérieure du substrat, entre la grille et la région de contact de drain 37. La couche 39 sert à protéger la zone d'extension de drain pendant une étape ultérieure de siliciuration. Au cours de l'étape de siliciuration, une couche de siliciure 41 est formée au-dessus des régions de source 35 et de contact de drain 37, et au-dessus des régions de contact 33. Afin de garantir que la partie de la zone d'extension de drain proche du bord de la grille 31 du côté du drain ne soit pas siliciurée, la couche 39 est formée de sorte qu'elle déborde sur le bord de la grille 31 du côté du drain. De même, afin de garantir que la partie de la zone d'extension de drain proche de la région de contact de drain 37 ne soit pas siliciurée, la couche 39 est formée de sorte qu'elle déborde sur la région de contact de drain 37. La couche 39 est formée en même temps qu'une couche isolante destinée à protéger d'autres régions du substrat vis-à-vis de l'étape de siliciuration. Un avantage du procédé de fabrication d'un transistor MOS à drain étendu décrit en relation avec les figures 2A à 2D réside dans le fait qu'il ne nécessite pas d'étape de fabrication supplémentaire par rapport aux étapes de fabrication de transistors MOS classiques (c'est-à-dire sans extension de drain) dans des technologies CMOS. Un transistor MOS à canal P à drain étendu du type illustré en figure 2D présente plusieurs avantages par rapport 30 aux transistors MOS à drain étendu connus. Un premier avantage est lié au fait que la zone d'extension de drain, constituée par le caisson PwellGO2 23, présente une profondeur élevée, par exemple de l'ordre de 1,5 à 2 pin, par rapport à la profondeur de la zone d'extension de 35 drain des transistors à extension de drain connus, par exemple B11376 - 11-GR3-0737FR01 11 de l'ordre de 0,15 pin. Il en résulte que la résistance d'accès au drain, et donc la résistance du transistor à l'état passant, est inférieure à celle des transistors MOS à drain étendu connus. En outre, si des porteurs chauds sont piégés à l'interface entre le caisson 23 et la couche 39, ceci induira une augmentation de la résistance d'accès au drain nettement inférieure à celle qui est observée dans le cas de transistors MOS à drain étendu connus. Un second avantage est lié au fait que la jonction P-N entre le caisson 25 et la zone d'extension de drain 23 n'est pas située sous le bord de la grille (côté drain). Il en résulte que le champ électrique à l'extrémité du canal, au niveau de la jonction P-N, est moins fort que si la jonction P-N était située sous le bord de la grille. L'injection de porteurs chauds dans l'isolant de grille 29 et dans la couche isolante 39 est ainsi réduite, et la durée de vie du transistor est améliorée. Des modes de réalisation particuliers de la présente invention ont été décrits. Diverses variantes et modifications apparaîtront à l'homme de l'art. En particulier, une variante du procédé de fabrication d'un transistor MOS à canal P à drain étendu décrit ci-dessus consiste à former, à l'étape illustrée en figure 2C, une région de source 35 plus complexe que celle illustrée en figure 2C, afin d'ajuster la tension de seuil du transistor. Pour cela, on forme, par exemple en même temps que dans les transistors PMOSGO1, une portion moins fortement dopée de type P à proximité de la grille dans la région de source, correspondant à la portion 20 illustrée en figure 1, et une poche de type N, plus fortement dopée que le caisson 25 NwellGO2, correspondant à la poche 21 illustrée en figure 1. During the step of forming the source 35 and drain contact 37 regions, P-type doping elements are also implanted in the gate 31. In order to guarantee that P-type doping elements are not implanted in the box 23 between the edge of the gate and the drain contact region 37, the resin 34 has been formed so that it overflows the edge of the gate 31 on the drain side. As a result, as shown in FIG. 2C, a portion 32 of the gate 31 (toward the edge of the gate, on the drain side) is not doped. The drain source and contact regions of the extended drain transistor are formed at the same time as the source and drain regions of the PMOSGO2 transistors. The N-type well 25 constitutes the body well of the extended drain P-channel transistor, in the upper part of which the channel of the transistor is formed. The channel extends under the gate from the edge of the source region 35 to the junction between the box 25 and the box 23. The box 23 constitutes the drain extension zone of the box. extended drain transistor. FIG. 2D illustrates a step of depositing a layer of an insulating material 39, for example silicon oxide, above the drain extension zone, that is to say on the upper surface of the substrate, between the gate and the drain contact region 37. The layer 39 serves to protect the drain extension zone during a subsequent siliciding step. During the siliciding step, a silicide layer 41 is formed above the source and drain contact regions 37 and above the contact regions 33. To ensure that the portion of the zone If the drain extension near the edge of the gate 31 on the drain side is not silicided, the layer 39 is formed so that it extends over the edge of the gate 31 on the drain side. Also, in order to ensure that the portion of the drain extension area near the drain contact region 37 is not silicided, the layer 39 is formed so that it overflows over the drain contact region 37 The layer 39 is formed at the same time as an insulating layer for protecting other regions of the substrate from the siliciding step. An advantage of the method for manufacturing an extended drain MOS transistor described in relation to FIGS. 2A to 2D lies in the fact that it does not require any additional manufacturing step compared to the conventional MOS transistor manufacturing steps ( that is, without drain extension) in CMOS technologies. An extended drain P-channel MOS transistor of the type illustrated in FIG. 2D has several advantages over known extended-drain MOS transistors. A first advantage is related to the fact that the drain extension zone, constituted by the PwellGO2 box 23, has a high depth, for example of the order of 1.5 to 2 pin, with respect to the depth of the zone. the drain extension of the known drain extension transistors, for example, of the order of 0.15 pin. As a result, the drain access resistance, and thus the resistance of the transistor in the on state, is lower than that of the known extended drain MOS transistors. In addition, if hot carriers are trapped at the interface between the box 23 and the layer 39, this will induce an increase in the drain access resistance significantly lower than that observed in the case of extended drain MOS transistors. known. A second advantage is related to the fact that the P-N junction between the box 25 and the drain extension zone 23 is not located under the edge of the gate (drain side). As a result, the electric field at the end of the channel, at the P-N junction, is less strong than if the P-N junction were below the edge of the gate. The injection of hot carriers into the gate insulator 29 and into the insulating layer 39 is thus reduced, and the lifetime of the transistor is improved. Particular embodiments of the present invention have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, a variant of the method for manufacturing an extended drain P-channel MOS transistor described above consists in forming, in the step illustrated in FIG. 2C, a source region 35 that is more complex than that illustrated in FIG. 2C. , in order to adjust the threshold voltage of the transistor. For this, one forms, for example at the same time as in the PMOSGO1 transistors, a less heavily doped P-type portion near the gate in the source region, corresponding to the portion illustrated in FIG. 1, and a pocket of FIG. N type, more heavily doped than the box NwellGO2, corresponding to the pocket 21 illustrated in Figure 1.

On a décrit ci-dessus un procédé de fabrication d'un transistor MOS à canal P à drain étendu utilisant principalement les étapes de fabrication de transistors MOS à canal P classiques (sans extension de drain) de type PMOSGO2, avec les modifications suivantes : B11376 - 11-GR3-0737FR01 12 former un caisson de type P (PwellGO2) juxtaposé à un caisson de corps de type N (NwellGO2) du transistor à drain étendu, le caisson de type P étant formé en même temps que des caissons de corps de type P de transistors NMOSGO2 ; et former une région de contact de drain dans le caisson de type P à distance de la jonction entre le caisson de type P et le caisson de type N. L'homme de l'art saura adapter le procédé décrit pour fabriquer un transistor MOS à canal P à drain étendu en utilisant principalement les étapes de fabrication de transistors MOS à canal P classiques (sans extension de drain) de type PMOSGO1, le caisson de corps de type N étant dans ce cas un caisson de type NwellGOl, et le caisson de type P étant par exemple un caisson de type PwellGOl. A method for manufacturing an extended drain P-channel MOS transistor has been described above, mainly using the fabrication steps of conventional P-channel MOS transistors (without drain extension) of the PMOSGO2 type, with the following modifications: B11376 - 11-GR3-0737EN01 12 forming a P-type well (PwellGO2) juxtaposed to an N-type body well (NwellGO2) of the extended-drain transistor, the P-type well being formed at the same time as the body wells. P type of NMOSGO2 transistors; and forming a drain contact region in the P-type well at a distance from the junction between the P-type well and the N-type well. Those skilled in the art will be able to adapt the described method for producing a MOS transistor to extended drain P channel mainly using the PMOSGO1-type conventional P-channel MOS transistors (without drain extension), the N type body box being in this case a NwellGO1 type box, and the box of type P being for example a PwellGOl type box.

Claims (11)

REVENDICATIONS1. Procédé de fabrication d'un transistor MOS à canal P à drain étendu, dans une filière technologique adaptée à la fabrication de transistors MOS à canal N (NMOSGO2 ; NMOSG01) et de transistors MOS à canal P (PMOSGO2 ; PMOSG01) dans un substrat semiconducteur, ce procédé utilisant essentiellement les étapes de fabrication de transistors à canal P avec les modifications suivantes : former un premier caisson (23) de type P juxtaposé à un second caisson (25) de corps de type N du transistor à drain 10 étendu, le premier caisson étant formé en même temps que des caissons de corps de type P de transistors à canal N ; et former une région de contact de drain (37) dans le premier caisson à distance de la jonction entre les premier et second caissons. 15 REVENDICATIONS1. Method for manufacturing an extended-drain P-channel MOS transistor in a technological pathway suitable for manufacturing N-channel MOS transistors (NMOSGO2; NMOSG01) and P-channel MOS transistors (PMOSGO2; PMOSG01) in a semiconductor substrate this method essentially employs the steps of manufacturing P-channel transistors with the following modifications: forming a first P-type well (23) juxtaposed with a second N-type body well (25) of the extended drain transistor 10, first well being formed at the same time as P-type body wells of N-channel transistors; and forming a drain contact region (37) in the first well away from the junction between the first and second wells. 15 2. Procédé selon la revendication 1, comprenant en outre une étape de formation d'une grille (31) s'étendant au-dessus d'une partie du second caisson (25) et d'une partie du premier caisson (23). The method of claim 1, further comprising a step of forming a grid (31) extending over a portion of the second well (25) and a portion of the first well (23). 3. Procédé selon la revendication 2, dans lequel la 20 région de contact de drain (37) du transistor à drain étendu est formée à distance de la grille (31). The method of claim 2, wherein the drain contact region (37) of the extended drain transistor is formed remote from the gate (31). 4. Procédé selon la revendication 3, comprenant en outre une étape de dépôt d'une couche d'un matériau isolant (39) au-dessus du substrat, entre la grille (31) et la région de 25 contact de drain (37), cette étape précédant une étape de siliciuration. The method of claim 3, further comprising a step of depositing a layer of insulating material (39) over the substrate between the gate (31) and the drain contact region (37). this step preceding a silicidation step. 5. Procédé selon l'une quelconque des revendications 1 à 4, dans lequel ladite filière est adaptée à la fabrication de transistors MOS d'une première épaisseur de grille (e2) et de 30 transistors MOS d'une seconde épaisseur de grille (el) inférieure à la première épaisseur. 5. Method according to any one of claims 1 to 4, wherein said die is suitable for manufacturing MOS transistors of a first gate thickness (e2) and 30 MOS transistors of a second gate thickness (el ) less than the first thickness. 6. Procédé selon la revendication 5, comprenant en outre une étape de formation d'une région de source (35) dans le second caisson (25), la région de source comportant une portionB11376 - 11-GR3-0737FR01 14 moins fortement dopée à proximité de la grille, et une étape de formation d'une poche de type N, plus fortement dopée que le second caisson, s'étendant autour de la région de source et de la portion moins fortement dopée, la portion moins fortement dopée et la poche de type N étant formées en même temps que des portions moins fortement dopées et des poches de type N dans des régions de source et de drain de transistors à canal P de la seconde épaisseur. The method of claim 5, further comprising a step of forming a source region (35) in the second well (25), the source region comprising a less heavily doped portion (25). proximity of the gate, and a step of forming an N-type pocket, more heavily doped than the second well, extending around the source region and the less heavily doped portion, the less heavily doped portion and the N-type pouch being formed at the same time as less heavily doped portions and N-type pockets in source and drain regions of P-channel transistors of the second thickness. 7. Procédé selon l'une quelconque des revendications 1 10 à 6, comprenant en outre une étape de formation d'une couche enterrée (27) de type N au-dessous du premier caisson. The method of any one of claims 1-10, further comprising a step of forming an N-type buried layer (27) beneath the first well. 8. Transistor MOS à canal P à drain étendu, comprenant : un premier caisson (23) de type P juxtaposé à un 15 second caisson de corps (25) de type N ; et une région de contact de drain (37) s'étendant dans le premier caisson à distance de la jonction entre le premier et le second caisson. An extended drain P-channel MOS transistor, comprising: a first P-type well (23) juxtaposed to a second N-type body well (25); and a drain contact region (37) extending into the first well away from the junction between the first and second wells. 9. Transistor MOS selon la revendication 8, comprenant 20 en outre une grille (31) s'étendant au-dessus d'une partie du second caisson (25) et d'une partie du premier caisson (23). 9. The MOS transistor of claim 8, further comprising a gate (31) extending over a portion of the second well (25) and a portion of the first well (23). 10. Transistor MOS selon la revendication 9, dans lequel la région de contact de drain (37) est formée à distance de la grille (31). 25 The MOS transistor of claim 9, wherein the drain contact region (37) is formed remote from the gate (31). 25 11. Dispositif de régulation de tension comportant un transistor MOS à canal P à drain étendu selon l'une quelconque des revendications 8 à 10. A voltage regulating device comprising an extended drain P-channel MOS transistor according to any one of claims 8 to 10.
FR1161807A 2011-12-16 2011-12-16 Extended drain P-channel metal-oxide-semiconductor transistor manufacturing method for voltage regulation device of mobile phone, involves forming drain contact area in P-type housing remote from P-type housing/N-type body housing junction Withdrawn FR2984596A1 (en)

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Publication number Priority date Publication date Assignee Title
US20060267116A1 (en) * 2005-05-24 2006-11-30 Yasuhiro Shimamoto Semiconductor device and manufacturing of the same
US20080023760A1 (en) * 2006-07-28 2008-01-31 Broadcom Corporation Semiconductor device with increased breakdown voltage
US20080087969A1 (en) * 2006-10-11 2008-04-17 Yong-Keon Choi Planar-type semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060267116A1 (en) * 2005-05-24 2006-11-30 Yasuhiro Shimamoto Semiconductor device and manufacturing of the same
US20080023760A1 (en) * 2006-07-28 2008-01-31 Broadcom Corporation Semiconductor device with increased breakdown voltage
US20080087969A1 (en) * 2006-10-11 2008-04-17 Yong-Keon Choi Planar-type semiconductor device and method of manufacturing the same

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