FR2982420A1 - Metal-oxide-semiconductor transistor, has semiconductor zones with same conductivity connected with same conductivity of drain and source areas, and extended in substrate so as to couple two adjacent portions of channel in electrically - Google Patents
Metal-oxide-semiconductor transistor, has semiconductor zones with same conductivity connected with same conductivity of drain and source areas, and extended in substrate so as to couple two adjacent portions of channel in electrically Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000003071 parasitic effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000011218 segmentation Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
B11-3091FR 1 Transistor MOS à grille de grande longueur.B11-3091EN 1 MOS transistor with a long gate.
L'invention concerne les transistors MOS (Metal Oxyde Semiconductor), et plus particulièrement les transistors à grille de grande longueur ou large grille. Les dimensions des transistors réalisés dans un substrat semiconducteurs sont actuellement limitées notamment en ce qui concerne les dimensions de la grille de commande. En effet, au-delà d'une certaine longueur, la grille peut se creuser lors des étapes de réalisation, par exemple lors d'un polissage mécanochimique, conduisant alors à l'obtention de grille d'épaisseur non homogène, plus fine au centre que sur son pourtour. Par exemple, dans le cas d'une technologie 20 nm, les règles de conception (DRM : Design Rules Manual selon un acronyme anglosaxon bien connu de l'homme du métier) imposent que la longueur de grille d'un transistor à large grille soit limitée à 2 um. En effet au-delà de cette valeur se produit un creusement de grille mentionnée ci-avant.The invention relates to MOS (Metal Oxide Semiconductor) transistors, and more particularly to gate transistors of great length or wide gate. The dimensions of the transistors made in a semiconductor substrate are currently limited in particular as regards the dimensions of the control gate. Indeed, beyond a certain length, the grid may widen during the production steps, for example during a mechanochemical polishing, leading then to obtaining a grid of non-homogeneous thickness, finer in the center only on its periphery. For example, in the case of a 20 nm technology, the design rules (DRM: Design Rules Manual according to an acronym well known to those skilled in the art) require that the gate length of a wide gate transistor is limited to 2 μm. Indeed beyond this value occurs a grid digging mentioned above.
Or certains circuits analogiques par exemple nécessitent d'avoir des transistors de longueurs de grilles importantes, typiquement supérieures à 2 um, par exemple égale à 4 um. Une solution pour obtenir une grille de longueur totale importante désirée consiste à connecter en série plusieurs transistors MOS ayant chacun une grille de longueur réduite (inférieure au seuil au-delà duquel peut se produire l'effet de creusement) et de connecter ensemble les différentes grilles. Cela étant ; les contacts nécessaires à la connexion électrique entre les régions de source et de drain de deux transistors adjacents génèrent des capacités parasites qui sont préjudiciables aux performances globales de l'ensemble ainsi réalisé, par exemple selon l'application envisagée, en termes de retards et bande passante. Selon un mode de réalisation, il est proposé un transistor MOS à grille isolée capable d'avoir une grille de dimension totale équivalente aussi grande que possible sans risque de creusement de la grille tout en conservant des performances acceptables pour le transistor. Selon un aspect, il est proposé, dans un mode de réalisation, un transistor MOS, qui peut être de type N ou de type P, comprenant au sein d'un substrat semi-conducteur, une région de source et une région de drain, ainsi qu'une grille isolée disposée au-dessus du substrat entre les régions de drain et de source. Selon une caractéristique générale, la grille est segmentée avec au moins deux segments de grille, chaque segment de grille étant apte à commander une portion de canal dans le substrat, tous les segments de grille étant électriquement reliés, et le transistor comprend en outre des zones semi-conductrices de liaison de même type de conductivité que celle des zones de drain et de source et s'étendant dans le substrat de manière à coupler électriquement deux portions de canal adjacentes.However, some analog circuits for example require having transistors of large grid lengths, typically greater than 2 μm, for example equal to 4 μm. One solution for obtaining a desired large total length grid consists of connecting in series a plurality of MOS transistors each having a reduced length gate (below the threshold beyond which the digging effect can occur) and of connecting the different gates together. . That being the case; the contacts necessary for the electrical connection between the source and drain regions of two adjacent transistors generate parasitic capacitances which are detrimental to the overall performances of the assembly thus produced, for example according to the application envisaged, in terms of delays and band bandwidth. According to one embodiment, there is provided an insulated gate MOS transistor capable of having a grid of equivalent total size as large as possible without risk of digging the gate while maintaining acceptable performance for the transistor. According to one aspect, it is proposed, in one embodiment, a MOS transistor, which may be N-type or P-type, comprising within a semiconductor substrate, a source region and a drain region, and an insulated gate disposed above the substrate between the drain and source regions. According to a general characteristic, the gate is segmented with at least two gate segments, each gate segment being able to control a channel portion in the substrate, all the gate segments being electrically connected, and the transistor further comprises zones connecting semiconductors of the same conductivity type as the drain and source areas and extending into the substrate to electrically couple two adjacent channel portions.
L'utilisation d'une grille segmentée permet ainsi d'augmenter la taille totale de la grille en évitant les risques de creusement de la grille. Ainsi dans une technologie 20 nm, chaque segment de grille a de préférence une longueur inférieure ou égal à 2 pm. Par ailleurs le transistor MOS est avantageusement exempt de contact sur le substrat entre les segments de grille. En effet l'utilisation d'une grille segmentée en combinaison avec les zones semi-conductrices de liaison s'étendant dans le substrat de manière à coupler électriquement deux portions de canal adjacentes, permet en outre de s'affranchir des contacts entre des transistors de l'art antérieur connectés en série, ce qui réduit les capacités parasites. Le fait d'avoir plusieurs segments de grille permet en outre d'améliorer certaines performances électriques du transistor MOS telles que notamment l'appariement (« matching » en langue anglaise) et les performances en courant continu (DC selon un acronyme anglosaxon bien connu de l'homme du métier) telles que la conductance de sortie (gds) et le gain intrinsèque du transistor (gm/gds). Les segments de grille peuvent avoir une longueur identique.The use of a segmented grid thus increases the total size of the grid avoiding the risk of digging the grid. Thus, in a 20 nm technology, each grid segment preferably has a length of less than or equal to 2 μm. Moreover, the MOS transistor is advantageously free of contact on the substrate between the gate segments. Indeed, the use of a segmented grid in combination with the semiconducting connection zones extending in the substrate so as to electrically couple two adjacent channel portions also makes it possible to overcome the contacts between transistors of the prior art connected in series, which reduces the parasitic capacitances. The fact of having several grid segments also makes it possible to improve certain electrical performances of the MOS transistor such as, in particular, matching ("matching" in English) and DC performance (DC according to a well-known English acronym for those skilled in the art) such as the output conductance (gds) and the intrinsic gain of the transistor (gm / gds). The grid segments can have an identical length.
Cela étant, avantageusement, au moins un segment de grille peut posséder une longueur différente des autres segments de grille. En effet une segmentation non constante de la grille (segments de longueurs différentes) est préférable à une segmentation constante de la grille (segments de longueurs identiques) en terme de performances DC et en terme de vitesse de transmission du signal dans le cas d'un transistor MOS de type P. Le segment de grille adjacent à la région de drain peut posséder une longueur plus petite que celle du segment de grille adjacent à la région de source. Ceci permet d'améliorer les performances DC dans le cas d'un transistor NMOS. En variante, le segment de grille adjacent à la région de source peut posséder une longueur plus petite que celle du segment de grille adj acent à la région de drain. Ceci permet d' améliorer les performances DC dans le cas d'un transistor PMOS. D' autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée d'un mode de réalisation, nullement limitatifs, et des dessins annexés sur lesquels les figures 1 et 2 représentent respectivement de manière schématique une vue de dessus et une vue en coupe selon la ligne II- Il' d'un mode de réalisation d'un transistor MOS selon l'invention. Le transistor MOS 1, par exemple un transistor MOS à canal N, comprend au sein d'un substrat 2 semi-conducteur, par exemple du silicium de type de conductivité P, une région de drain 3 et une région de source 4 toutes deux de type de conductivité N. La région de drain 3 est typiquement reliée via un premier contact électrique 5 à une source d'alimentation Vdd, et la région de source 4 est reliée via un second contact électrique 6 à la masse GND. Le transistor MOS comprend une grille 7 isolée disposée au- dessus du substrat 2 semi-conducteur entre la région de source 3 et la région de drain 4. La grille 7 comprend une pluralité de segments 8 de grille, par exemple en polysilicium, électriquement reliés ensemble par exemple via des contacts 11 et une piste métallique d'un niveau de métallisation d'un circuit intégré incorporant le transistor. La métallisation peut ainsi former l'entrée de signal In du transistor et la région de drain 3 peut former la sortie de signal Out.However, advantageously, at least one grid segment may have a length different from the other grid segments. Indeed a non-constant segmentation of the gate (segments of different lengths) is preferable to a constant segmentation of the gate (segments of identical lengths) in terms of DC performance and in terms of signal transmission speed in the case of a P-type MOS transistor. The gate segment adjacent to the drain region may have a smaller length than the gate segment adjacent to the source region. This makes it possible to improve the DC performance in the case of an NMOS transistor. Alternatively, the gate segment adjacent to the source region may have a smaller length than that of the gate segment adjacent to the drain region. This makes it possible to improve DC performance in the case of a PMOS transistor. Other advantages and features of the invention will appear on examining the detailed description of an embodiment, which are in no way limiting, and the appended drawings in which FIGS. 1 and 2 respectively show schematically a view from above and a sectional view along line II-II 'of an embodiment of a MOS transistor according to the invention. The MOS transistor 1, for example an N-channel MOS transistor, comprises, within a semiconductor substrate 2, for example silicon of conductivity type P, a drain region 3 and a source region 4 both of type of conductivity N. The drain region 3 is typically connected via a first electrical contact 5 to a power source Vdd, and the source region 4 is connected via a second electrical contact 6 GND ground. The MOS transistor comprises an insulated gate 7 disposed above the semiconductor substrate 2 between the source region 3 and the drain region 4. The gate 7 comprises a plurality of electrically connected grid segments 8, for example made of polysilicon. together for example via contacts 11 and a metal track of a metallization level of an integrated circuit incorporating the transistor. The metallization can thus form the signal input In of the transistor and the drain region 3 can form the signal output Out.
Chaque segment de grille 8 est isolée de la portion de substrat sous-jacente par un oxyde de grille 10, par exemple du dioxyde de silicium. Chaque segment de grille est par ailleurs flanqué de façon classique d'espaceurs isolants 15.Each gate segment 8 is isolated from the underlying substrate portion by a gate oxide 10, for example silicon dioxide. Each grid segment is also flanked conventionally with insulating spacers 15.
Chaque segment 8 de grille commande une portion de canal 14 formée dans le substrat. Des zones de liaisons 9, de même type de conductivité que la zone de source 3 et la zone de drain 4, sont formées dans le substrat, typiquement par implantation, de manière à électriquement coupler deux portions de canal adjacentes 14. L'assemblage de segments 8 de grille pour réaliser une grille de transistor permet de concevoir un transistor MOS à large grille dont la taille de grille n'est pas limitée tout en respectant les règles de conception (DRM) imposées par la technologie.Each gate segment 8 controls a channel portion 14 formed in the substrate. Binding zones 9, of the same conductivity type as the source zone 3 and the drain zone 4, are formed in the substrate, typically by implantation, so as to electrically couple two adjacent channel portions 14. Grid segments 8 for making a transistor gate makes it possible to design a wide-gate MOS transistor whose grid size is not limited while respecting the design rules (DRM) imposed by the technology.
L'espace entre deux espaceurs voisins est réduit et les zones de liaison 9 semi-conductrices permettent d'éviter l'utilisation de contacts métalliques entre les segments 8 de grille pouvant générer des capacités parasites préjudiciables. Comme cela est représenté sur les figures 1 et 2, les segments 8 de grille peuvent posséder des longueurs Li différentes. La longueur totale Lt de la grille est égale à la somme des longueurs Li. La longueur maximale d'un segment de grille est inférieure à un seuil choisi en fonction de la technologie (limite technologique).The space between two neighboring spacers is reduced and the semiconductor bonding zones 9 make it possible to avoid the use of metal contacts between the gate segments 8 that can generate harmful parasitic capacitances. As shown in Figures 1 and 2, the gate segments 8 may have different lengths Li. The total length Lt of the grid is equal to the sum of the lengths Li. The maximum length of a grid segment is less than a threshold chosen according to the technology (technological limit).
Ce seuil est notamment fixé par les règles de conception (DRM) propres à la technologie utilisée, de façon en particulier à éviter un phénomène de creusement de la grille lors de la fabrication. Ainsi pour une technologie de 20 nm, la longueur maximale d'un segment de grille est égale à 2 i.tm.This threshold is in particular fixed by the design rules (DRM) specific to the technology used, in particular to avoid a phenomenon of digging of the grid during manufacture. Thus for a 20 nm technology, the maximum length of a grid segment is equal to 2 i.tm.
A titre d'exemple non limitatif, si l'on souhaite réaliser un transistor ayant une grille de longueur totale de 4 i.tm, on pourra utiliser par exemple quatre segments de grille ayant respectivement des longueurs égales à 0,25 µm ; 0,75 µm ; 1 µm ; 2 i.tm, ou bien quatre segments de longueur égales à 1 i.tm. En utilisant des segments 8 de grille de longueurs différentes, certaines performances (de transmission ou DC selon le type de transistor) sont augmentées par rapport à un transistor à grille segmentée comportant des segments de longueur constante.By way of nonlimiting example, if it is desired to produce a transistor having a gate of total length of 4 μm, it will be possible to use, for example, four gate segments having respective lengths equal to 0.25 μm; 0.75 μm; 1 μm; 2 i.tm, or four segments of length equal to 1 i.tm. By using gate segments 8 of different lengths, certain performances (transmission or DC depending on the type of transistor) are increased with respect to a segmented gate transistor having segments of constant length.
Le segment le plus court est ici placé du côté drain. Le fait que le segment de grille adjacent à la région de drain possède une longueur plus petite que celle du segment de grille adjacent à la région de source permet d'améliorer les performances DC du transistor NMOS.The shortest segment is here placed on the drain side. The fact that the gate segment adjacent to the drain region has a smaller length than that of the gate segment adjacent to the source region improves the DC performance of the NMOS transistor.
En variante, le segment de grille adjacent à la région de source peut posséder une longueur plus petite que celle du segment de grille adjacent à la région de drain. Ceci permet d'améliorer les performances DC dans le cas d'un transistor PMOS.Alternatively, the gate segment adjacent to the source region may have a smaller length than that of the gate segment adjacent to the drain region. This makes it possible to improve the DC performance in the case of a PMOS transistor.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1159952A FR2982420A1 (en) | 2011-11-03 | 2011-11-03 | Metal-oxide-semiconductor transistor, has semiconductor zones with same conductivity connected with same conductivity of drain and source areas, and extended in substrate so as to couple two adjacent portions of channel in electrically |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1159952A FR2982420A1 (en) | 2011-11-03 | 2011-11-03 | Metal-oxide-semiconductor transistor, has semiconductor zones with same conductivity connected with same conductivity of drain and source areas, and extended in substrate so as to couple two adjacent portions of channel in electrically |
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| Publication Number | Publication Date |
|---|---|
| FR2982420A1 true FR2982420A1 (en) | 2013-05-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| FR1159952A Withdrawn FR2982420A1 (en) | 2011-11-03 | 2011-11-03 | Metal-oxide-semiconductor transistor, has semiconductor zones with same conductivity connected with same conductivity of drain and source areas, and extended in substrate so as to couple two adjacent portions of channel in electrically |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256692A1 (en) * | 2003-06-19 | 2004-12-23 | Keith Edmund Kunz | Composite analog power transistor and method for making the same |
| US20080121997A1 (en) * | 2006-07-19 | 2008-05-29 | Hongning Yang | Multi-gate semiconductor device and method for forming the same |
| US20090212854A1 (en) * | 2008-02-25 | 2009-08-27 | Peter Baumgartner | Asymmetric Segmented Channel Transistors |
-
2011
- 2011-11-03 FR FR1159952A patent/FR2982420A1/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040256692A1 (en) * | 2003-06-19 | 2004-12-23 | Keith Edmund Kunz | Composite analog power transistor and method for making the same |
| US20080121997A1 (en) * | 2006-07-19 | 2008-05-29 | Hongning Yang | Multi-gate semiconductor device and method for forming the same |
| US20090212854A1 (en) * | 2008-02-25 | 2009-08-27 | Peter Baumgartner | Asymmetric Segmented Channel Transistors |
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| Date | Code | Title | Description |
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| ST | Notification of lapse |
Effective date: 20150731 |