FR2971596B1 - Dispositif pour accelerer l'execution d'une simulation systemc - Google Patents

Dispositif pour accelerer l'execution d'une simulation systemc

Info

Publication number
FR2971596B1
FR2971596B1 FR1151223A FR1151223A FR2971596B1 FR 2971596 B1 FR2971596 B1 FR 2971596B1 FR 1151223 A FR1151223 A FR 1151223A FR 1151223 A FR1151223 A FR 1151223A FR 2971596 B1 FR2971596 B1 FR 2971596B1
Authority
FR
France
Prior art keywords
execution
simulation
accelerating
systemc
processing units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1151223A
Other languages
English (en)
Other versions
FR2971596A1 (fr
Inventor
Nicolas Ventroux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1151223A priority Critical patent/FR2971596B1/fr
Priority to US13/984,525 priority patent/US9612863B2/en
Priority to PCT/EP2012/052386 priority patent/WO2012110445A1/fr
Publication of FR2971596A1 publication Critical patent/FR2971596A1/fr
Application granted granted Critical
Publication of FR2971596B1 publication Critical patent/FR2971596B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

La présente invention concerne un dispositif pour accélérer, sur une plateforme comportant une pluralité d'unités de traitement, l'exécution d'une simulation SystemC d'un système, ladite simulation comportant un noyau SystemC et des processus SystemC. Le dispositif comporte des moyens matériels pour ordonnancer les processus SystemC sur les unités de traitements de manière dynamique pendant l'exécution de la simulation, ces moyens permettant notamment de préempter les unités de traitement. Application : outils de vérification et d'émulation de circuits complexes
FR1151223A 2011-02-15 2011-02-15 Dispositif pour accelerer l'execution d'une simulation systemc Expired - Fee Related FR2971596B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1151223A FR2971596B1 (fr) 2011-02-15 2011-02-15 Dispositif pour accelerer l'execution d'une simulation systemc
US13/984,525 US9612863B2 (en) 2011-02-15 2012-02-13 Hardware device for accelerating the execution of a systemC simulation in a dynamic manner during the simulation
PCT/EP2012/052386 WO2012110445A1 (fr) 2011-02-15 2012-02-13 Dispositif pour accélérer l'exécution d'une simulation system c

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1151223A FR2971596B1 (fr) 2011-02-15 2011-02-15 Dispositif pour accelerer l'execution d'une simulation systemc

Publications (2)

Publication Number Publication Date
FR2971596A1 FR2971596A1 (fr) 2012-08-17
FR2971596B1 true FR2971596B1 (fr) 2016-01-01

Family

ID=45855711

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1151223A Expired - Fee Related FR2971596B1 (fr) 2011-02-15 2011-02-15 Dispositif pour accelerer l'execution d'une simulation systemc

Country Status (3)

Country Link
US (1) US9612863B2 (fr)
FR (1) FR2971596B1 (fr)
WO (1) WO2012110445A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3002342B1 (fr) * 2013-02-15 2015-02-27 Commissariat Energie Atomique Dispositif et procede pour accelerer la phase de mise a jour d'un noyau de simulation
US9817771B2 (en) * 2013-08-20 2017-11-14 Synopsys, Inc. Guarded memory access in a multi-thread safe system level modeling simulation
US9778817B2 (en) 2013-12-31 2017-10-03 Findo, Inc. Tagging of images based on social network tags or comments
US10445445B2 (en) * 2016-04-22 2019-10-15 Synopsys, Inc. Sliding time window control mechanism for parallel execution of multiple processor core models in a virtual platform simulation
US12032932B2 (en) * 2022-07-11 2024-07-09 Xilinx, Inc. Compiler-based generation of transaction accurate models from high-level languages

Family Cites Families (21)

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US7003441B2 (en) * 2001-07-31 2006-02-21 Hewlett-Packard Development Company, L.P. Method for deriving the benchmark program for estimating the maximum power consumed in a microprocessor
US20050229170A1 (en) * 2004-04-08 2005-10-13 Matthew Bellantoni Optimized system-level simulation
WO2006072082A2 (fr) * 2004-12-30 2006-07-06 Vast Systems Technology Corporation Systeme et procede de simulation d'horloge
JP2008059192A (ja) * 2006-08-30 2008-03-13 Oki Electric Ind Co Ltd ハード・ソフト協調検証用シミュレータ
US8296741B1 (en) * 2007-03-05 2012-10-23 Google Inc. Identifying function-level code dependency by simulating runtime binding
CN100580630C (zh) 2007-12-29 2010-01-13 中国科学院计算技术研究所 满足SystemC语法要求的多核处理器及获得其执行代码的方法
US7957950B2 (en) * 2008-02-28 2011-06-07 Oki Semiconductor Co., Ltd. Hard/soft cooperative verifying simulator
WO2009118731A2 (fr) * 2008-03-27 2009-10-01 Rocketick Technologies Ltd Simulation de conception utilisant des processeurs parallèles
JP5066013B2 (ja) * 2008-06-24 2012-11-07 富士通セミコンダクター株式会社 シミュレーション装置およびプログラム
CN101329702A (zh) 2008-07-22 2008-12-24 中国科学院计算技术研究所 一种满足SystemC语法的多核处理器的先进先出队列单元组
CN101634979B (zh) 2008-07-22 2011-09-07 中国科学院计算技术研究所 一种满足SystemC语法的多核处理器
CN101635006B (zh) 2008-07-22 2012-02-29 中国科学院计算技术研究所 一种满足SystemC语法的多核处理器的互斥和信号量单元组
CN100568247C (zh) 2008-07-22 2009-12-09 中国科学院计算技术研究所 一种满足systemC语法的多核处理器的事件处理单元组
US8156458B2 (en) * 2008-08-29 2012-04-10 International Business Machines Corporation Uniquification and parent-child constructs for 1xN VLSI design
CN101770362B (zh) 2009-01-06 2013-04-03 中国科学院计算技术研究所 满足SystemC的处理器中的分布式动态进程生成单元
JP5262774B2 (ja) * 2009-02-03 2013-08-14 富士通株式会社 シミュレーション制御プログラム、シミュレーション装置、およびシミュレーション制御方法
JP2012509546A (ja) * 2009-12-23 2012-04-19 インチロン ゲーエムベーハー 組み込みシステムをシミュレートするための方法及びデータ処理システム
US20110307847A1 (en) * 2010-06-10 2011-12-15 Global Unichip Corporation Hybrid system combining TLM simulators and HW accelerators
US8458630B1 (en) * 2010-06-26 2013-06-04 Cadence Design Systems, Inc. Supporting dynamic aspects of polymorphism in high-level synthesis of integrated circuit designs
US9015649B2 (en) * 2010-07-19 2015-04-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for electronic system model generation
US20120197625A1 (en) * 2011-01-28 2012-08-02 National Tsing Hua University Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling

Also Published As

Publication number Publication date
US9612863B2 (en) 2017-04-04
FR2971596A1 (fr) 2012-08-17
WO2012110445A1 (fr) 2012-08-23
US20140325516A1 (en) 2014-10-30

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