FR2965373A1 - Method for communication between master and slave circuits on open drain bus in master-slave transmission system, involves simultaneously transmitting opposite identifiers, where each slave circuit exploits combinations to determine order - Google Patents

Abstract

The method involves simultaneously transmitting identifiers (UID1, UID2) and reverse identifiers (NUIDI, NUID2) at same time by slave circuits, where each slave circuit exploits combinations present on bus for determining a communication order between the slave circuits. Preceding steps are triggered by a master circuit by sending a specific command on bus. The command is preceded by sending slave address (ADD1) common to the slave circuits. Relation i.e. order relation, between one of the identifiers of the slave circuit and another identifier of another slave circuit is determined. Independent claims are also included for the following: (1) a master-slave transmission system, comprising an electronic transmission circuit to implement (2) a method of communication between a master circuit and slave circuit.

Description

FIELD OF THE INVENTION The present invention relates to electronic transmissions and, more particularly, to the transmission of digital data in a master system. -slave. The invention applies more particularly to communications on a bus, said open-drain or open collector (according to MOS or bipolar technology), according to a protocol where the transmission speed is independent of the states of the transmitted bits. The invention applies, for example, to two-wire bus transmissions conveying data and a synchronization signal, for example of the I2C type. DISCUSSION OF THE PRIOR ART In an open-drain bus (or open collector), the data conductor of the bus is, at rest, at a potential different from the ground (generally a positive potential). The data is encoded and then transmitted by pulling the bus to ground according to a pre-established encoding enabling the receiver to decode the data. Many communication protocols are known operating an open drain bus (or open collector). Be it single-wire bus protocols (for example, a B10602 - 10-RO-292

2 protocol known under the name SWP) or on a multi-wire bus (for example, two-wire type I2C protocols), when several slave circuits are connected on the same bus and are capable of communicating with the same master circuit, the master circuit must send on the bus an address or an identifier of the slave circuit allowing it to recognize and respond. Other slave circuits that do not recognize themselves from the address remain silent.

In the usual systems, it is therefore necessary for the master circuit to know the addresses of the different slave circuits, otherwise several slave circuits may respond at the same time, which renders the transmission uninterpretable.

SUMMARY An object of an embodiment of the present invention is to overcome all or part of the disadvantages of communication systems on open drain bus (or open collector).

Another object of an embodiment of the present invention is to allow two slave circuits to identify themselves to a master circuit. Another object of an embodiment of the present invention is to propose a solution more particularly intended for communication protocols in which bits are transmitted over periods of durations independent of the respective states of the bits. Another object of an embodiment of the present invention is to propose a solution allowing simultaneous communication between a master circuit and two slave circuits. To achieve all or part of these objects as well as others, there is provided a method of communication between a master circuit and two slave circuits on a serial bus in which: B10602 - 10-RO-292

The two slave circuits at the same time transmit identifiers associated with them; the two slave circuits transmit at the same time the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine a communication order between the two circuits. According to one embodiment of the present invention, the master circuit triggers the preceding steps by sending a specific command on the bus. According to one embodiment of the present invention, said command is preceded by the sending by the master circuit of an address common to the two slave circuits. According to an embodiment of the present invention, each slave circuit determines a relationship between its own identifier and that of the other slave circuit. According to an embodiment of the present invention, the relationship between the identifiers is a relation of order. According to an embodiment of the present invention, each slave circuit transmits, to the master circuit, an address relating to it, the transmission order being fixed by the relation between the respective identifiers of the slave circuits. According to an embodiment of the present invention, each slave circuit transmits, to the master circuit, its identifier as an address. According to one embodiment of the present invention, the bus is an open drain bus (or open collector) in which a bit is transmitted over a period of time independent of the state of the bit. An electronic circuit for transmission over a serial bus is also provided. There is also provided a master-slave transmission system between a master and two slaves.

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BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages will be set forth in detail in the following non-limiting description of particular embodiments in connection with the accompanying figures in which: FIG. partially and in the form of blocks, two circuits capable of communicating in a master-slave I2C protocol; Figures 2A, 2B, 2C and 2D illustrate a communi-10 cation between the two circuits of Figure 1; Fig. 3 schematically shows in block form an example of a communication system according to an embodiment of the present invention; FIG. 4 illustrates a usual communication frame according to the I2C protocol; FIG. 5 very schematically represents the data conductor of an open-drain bus (and open collector) and its connections in a system of the type of FIG. 3; FIG. 6 very schematically illustrates in block form an embodiment of the method of identifying slave circuits by a master circuit according to an embodiment of the present invention; Figure 7 illustrates a frame according to the method of Figure 6; and Fig. 8 is a timing diagram illustrating an example of a communication protocol to which the present invention applies. DETAILED DESCRIPTION The same elements have been designated with the same references in the various figures. For the sake of clarity, only the steps and elements useful for understanding the exposed embodiments will be described. In particular, the exploitation of the data in each of the communicating circuits has not been detailed, the embodiments B10602-10-RO-292

described being compatible with the usual uses of these data. In addition, the coding of the signals to be transmitted by the various communicating circuits has not been detailed either, the invention being again compatible with conventional coding circuits for such signals. Embodiments will subsequently reference a communication exploiting the functionality of a protocol known as I2C. The invention more generally applies to any communication protocol using at least one data transmission wire in an open-drain protocol (or open collector), and in which the durations of the periods on which the bits are transmitted are independent. of their states (the transmission of a 1 occupies the same duration as the transmission of a 0).

FIG. 1 is a block diagram of an embodiment of a communication system between a master device 1 and a slave device 3 according to the I2C protocol. In the example of FIG. 1, the circuit 1 is a master circuit (MD) and is capable of communicating, via an I2C bus, with one or more slave devices 3 (SD). The various circuits of the system may be powered independently of each other or, as shown, by a power supply bus capable of carrying at least one VDD supply potential and a reference potential (GND), for example ground . Each circuit 1, 3 comprises, for example, a transmission circuit (SEND) 11, 31 and a receiving circuit (DEI) 12, 32. The circuits 1 and 3 are connected to each other by the bus I2C as well as the two VDD and GND wires of the power bus. A first wire 42 of the I2C bus carries a clock signal (SCL) between two terminals CK circuits 1 and 3. Typically, this clock signal is imposed by the master circuit 1. A second wire 44 of the I2C bus conveys the data (SDA) between the two circuits. The I2C bus is bidirectional.

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FIGS. 2A, 2B, 2C and 2D are timing diagrams illustrating an example of transmission of a data word (typically a byte) from the master circuit to the slave circuit 3.

To clarify the description, FIGS. 2A, 2B, 2C and 2D show the signal curve corresponding respectively to the signal (SDAM) set by the transmission circuit 11 of the master circuit on the wire 44, to the clock signal (SCL ) imposed by the master circuit, the signal (SDAS) positioned by the circuit 31 on the wire 44, and the (SDA) resulting from this wire. Despite the simplified representation of FIG. 1, it is considered that the respective reception circuits 12 and 32 of the circuits 1 and 3 observe the state of the wire 44 independently of the imposed levels SDAM and SDAS by their transmission circuits 11 and 31. even, for simplicity, we neglect the voltage drops with respect to the supply potential and we consider that the high levels correspond to the voltage VDD and that the low levels correspond to the mass.

At rest, the two son 42 and 44 of the bus I2C are high. This is what characterizes a so-called open-drain bus (or open collector) where the bus is pulled to the supply voltage and is then forced to a lower state (in this example, ground) by the different communicating devices. Assuming that the circuit wants to transmit a data frame to the circuit 3, it takes control of the bus by imposing a low level on the SDA signal (time t1) while the SDL signal remains high. This start condition is detected by the slave circuit 3 connected on the bus. Once this initial condition is completed, the circuit 1 generates the clock signal SCL. Then, the circuit 1 imposes a level 1 or 0 on the wire 44 (SDAM and SDA signals) as a function of the first bit D7 of the byte to be transmitted. This positioning of the wire 44 must take place before the rising edge of the signal B10602 - 10-RO-292

7 clock (time t2) that validates the data transmitted. When the signal SCL returns to the low level (time t3), the master circuit can impose the level corresponding to the state of the next bit D6 on the wire 44, and so on. Once the last bit DO has been transmitted, the master circuit places the SDAM signal high, to monitor the arrival of an acknowledgment. Its detection circuit 12 simultaneously monitors the actual state of the wire 44. To indicate a correct reception, the slave circuit 3 imposes a low level (FIG. 2C) on the wire 44 (SDAS and SDA signals). The master circuit checks the state of the wire 44 at the rising edge (time t4) of the SCL signal which follows its position in the high state of the SDAM signal. If the wire 44 is low (as shown in Figure 2), it means a successful transmission. In the opposite case, the master circuit can re-transmit the data (a start condition must be sent on the I2C bus). A transmission end (bus release) is performed by the master circuit by switching the SDA signal high while the SCL signal is also high (instant t5). Once this Stop condition has been completed, the I2C bus is free to start another I2C frame. It may be, for example, a transmission of the circuit 3 to the circuit 1. The communication protocol I2C sets different additional conditions in the transmission depending on whether it relates to an address, data, writing or reading in the slave circuit, etc. In particular, an address is generally provided when several slave circuits are likely to be connected on the same bus.

FIG. 3 very schematically shows in the form of blocks an example of a master-slave transmission system in which a master circuit 1 is capable of communicating with two slave circuits 3 (S1) and 3 '(S2), and if necessary with still other slave circuits connected on the I2C bus. To simplify the representation of Figure B10602 - 10-RO-292

8 3, it was considered that slave circuits were powered separately and individually with respect to each other. FIG. 4 very schematically shows a usual transmission frame T according to the I2C protocol. Following the start bit (S in FIG. 4), the master circuit sets the address of a slave circuit (Slave address) on the I2C bus. Generally, this address is on one or two bytes but any other configuration may be suitable. The address is followed by an R / W bit indicating to the slave circuit concerned whether the master wishes to write or retrieve data therein. This R / W bit is followed by an acknowledgment bit A positioned by the slave circuit concerned (symbolized with hatching to make it stand out that it comes from the slave circuit). Then, the master circuit sends bytes of data D1, ..., Dn, each followed by an acknowledgment from the slave circuit. Here we assume the sending of data from the master to the slave. In the case of a data recovery, the slave circuit sends the data and the master circuit acknowledges receipt at the end of each byte. The transmission ends with the P stop bit.

This system works properly provided that the master circuit is able to address a single slave circuit at a given time. In fact, in the opposite case, two slave circuits consider themselves addressed, which generates a conflict on the bus.

However, in some applications, slave circuits may be connected to the bus while the master circuit does not know the address. An example of application concerns the case of electronic devices in which two slave circuits may be connected on the same serial bus and must be accessible by a master circuit. This is the case, for example, of a system in which several power supply batteries of an electronic device may be connected to the same bus for authentication.

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The invention will be described later with particular reference to an I2C bus. It will be noted, however, that it applies more generally to any communication between a master circuit and several slave circuits on an open-drain (or open collector) type serial bus, in which the transmission period of a bit is the same. whatever the state of this bit. FIG. 5 schematically and partially shows a serial bus 44 (for example the SDA conductor of an I2C bus) and its connections to a master circuit 1 and to two slave circuits 3 and 3 '. Each circuit 1, 3, 3 'comprises a switch 14, 34 or 34' connecting a terminal, respectively 15, 35 or 35 ', to be connected to the bus 44. Moreover, as already mentioned, the driver 44 is, at rest, pulled to the potential VDD, for example by a resistive element R. In practice, the switches 14, 34 and 34 'are most often made in the form of N-channel MOS transistors, which is why reference to an open-drain serial bus (or open collector). The switch 14 of the master circuit 1 is controlled by its transmission circuit 11 (not shown in FIG. 5). The switches 34 and 34 'of the circuits 3 and 3' are respectively controlled by the transmission circuits 31 and 31 '(SEND). As already illustrated in connection with FIG. 1, the terminals 35 and 35 'are furthermore connected to the input of detectors 32 and 32' (DET) enabling each slave circuit to decode the signals present on the bus. The representation of FIG. 5 is partial and other circuits, in particular for processing the data transmitted and transmitted, equip the master and slave devices.

To be able to communicate with the two slave circuits, the master circuit 1 needs to identify them in order to address the frames that concern them respectively. In the embodiment of FIG. 5, it is assumed that both slave circuits 3 and 3 'share the same address B10602 - 10-RO-292

10 and are therefore, when connected to the bus, not identifiable by the master circuit. For example, there are two different batteries that need to be authenticated by the master circuit. It may also be other consumables like ink cartridges connected to the same bus. More generally, this embodiment applies as soon as two slave circuits are likely to be connected on the bus being addressed by means of the same address by the master circuit.

In a simplified embodiment where only two slave circuits are connected on the bus, this amounts to being able to connect, on this bus, two slave circuits without address. Figure 6 is a simplified flowchart illustrating a mode of identification by a master circuit of two slave circuits sharing the same address. Figure 7 illustrates an example of a communication frame corresponding to this identification process. In a first optional step (block 41, SEND 20 SA), the master circuit M sends, on the bus, the address corresponding to the two slave circuits. This address (block 42, SA) has slaves S1 and S2, on the bus is detected by the circuits which causes them to wake up (blocks 43 and 43 ', 25 WUP) or correspond connected to one or two slave circuits. The master circuit then sends an activation command. In practice, this address can be that of a bus port on which can be requested identifier (block 44, GET UID). In the simplified embodiment where only two slaves are connected on the bus, steps 41 and 42 can be omitted and sending command 44 causes the two slave circuits connected on the bus to wake up. As shown in FIG. 7, from the point of view of the communication frame, the master circuit initiates as previously a communication using a start bit S, B10602-10-RO-292

11 then sends the address of the slave. The protocol can be modified here with respect to a conventional I2C process insofar as the R / W bit is not necessary for the identification phase. Preferably, the master circuit waits for an acknowledgment bit A, even if it is not able to identify which of the slave circuits that sent it. This tells us at least that these slave circuits have had time to be activated. The master circuit then sends the command GET UID and detects a corresponding acknowledgment, again coming from one or the other or both slave circuits. Each circuit S1, S2 then sends on the bus a unique identifier concerning it (block 45, UID1 and block 45 ', UID2). This identifier is unique in that it must make it possible to distinguish the slave circuit from any other slave circuit that can be connected to the port accessible by the address AD. Such an identifier is, for example, stored in non-volatile memory during manufacture of the slave circuit. In the example of Figure 7, it is assumed that the identifier is eight bytes (BO to B7). From the point of view of the I2C bus, the sending of the two identifiers results in a combination of AND type (AND) of these identifiers. Indeed, if the current bit of one of the identifiers is a state 1, that is to say the high level VDD, the corresponding switch 34 or 34 'remains open. If the current bit is a state 0, switching of the switch 34 or 34 'forces the state of the bus to ground. Therefore, the 0 overrides the 1. It will be noted that the assignment of a value of 0 or 1 of the bit of the identifier with respect to the high or low potential is a convention, the combination operated on the bus so automatic, therefore, according to the adopted convention, to an AND or to a logical OR. This bitwise addition of identifiers is useless to the master circuit. However, it may, if necessary, send an acknowledgment bit (block 47, ACK). This allows, the case B10602 - 10-RO-292

12 to synchronize the transmission. On the other hand, each slave circuit receives the combination UID1 * UID2 and stores it. Then, each slave circuit S1 and S2 sends (block 48 and 48 ') the inverse NUID1, respectively NUID2, of its identifier. This results in the bus a logical combination of the NOR type (or NAND according to the coding) of the identifiers (block 49, NUID1 * NUID2). In a manner similar to the transmission of non-inverted identifiers, the master circuit may send an acknowledgment (block 50, ACK). The slave circuits 3 and 3 'memorize the combination of inverted identifiers. Each slave circuit, knowing its own identifier, the combination of this identifier with the identifiers of the other slave circuit and the combination of the respective inverse of these identifiers, decodes (block 51, DECOD UID2 and block 51 'DECOD UID1). identifier of the other slave circuit. The master circuit still knows neither of the identifiers. However, each slave circuit knows the identifier of the other. It is then possible to implement a determination rule (blocks 52 and 52 ', CHECK RULE) of the slave circuit to which a given address is assigned, or more generally a communication command between the two slave circuits. In the example of FIG. 6, the communication protocol sets a rule according to which the slave circuit having the smallest value identifier (for example the circuit S1) first transmits its address (block 53, ADD1) to the master circuit. The slave circuit S2 is placed on hold (block 54, WAIT) to transmit its address (block 53 ', ADD2) to the master circuit. It detects for example the acknowledgment of the first address by the master circuit. Consequently, the master circuit successively receives the address ADD1 that it memorizes (block 55, STORE ADD1) B10602 - 10-RO-292

13 and the ADD2 address that it stores (block 56, STORE ADD2). Once this initialization phase has been completed, the master circuit is able to send messages either to the slave circuit S1 or to the slave circuit S2.

ADD1 and ADD2 addresses should be different from each other. For example, a dynamic allocation based on an established convention is provided taking into account the order between the UIDs. The addresses can also be sent by the master circuit and taken into account by the slave circuits according to the established convention. According to another exemplary embodiment, the entire identifier UID1 and UID2 is transmitted to the master circuit. This transmission can be performed successively by each slave circuit or alternately, one byte by two, direction of the master circuit. According to an alternative embodiment, the identifier bytes are sent successively and alternately by each slave. It can thus be provided that the acknowledgment bit is sent by the slave circuits and not by the master circuit. The latter can, however, verify the individual behavior of each slave circuit by monitoring that at the end of each byte transmission, an acknowledgment bit is present on the bus. According to yet another example, the address simply corresponds to a bit 0 or 1 insofar as it is sufficient for the master circuit to be able to distinguish, when sending its frames, whether they are intended for the a two slave circuits. If other slave circuits are likely to be connected to the bus, this additional bit completes the address SA or replace a bit. The decoding by each of the slave circuits of the identifier of the other (blocks 51 and 51 ') can be carried out at the end of the reception of the combinations 46 and 49 or, alternatively, as and when if each slave circuit transmits B10602 - 10-RO-292

14 successively a byte of its identifier and the same inverted byte. In this case, the decoding is faster. According to another variant, the decoding is stopped as soon as a bit differs in the identifiers transmitted by the slave circuits. This is sufficient to apply a rule setting which circuitry first sends a response to the master circuit. It is also possible to alternate the transmission of identifiers and their inverses, bit by bit. Thus, the storage space needed is minimized. According to yet another variant, no address is transmitted to the master circuit and the latter simply communicates with the two slave circuits in a determined order. The slave circuits having mutually identified with each other, each one is capable, by applying the shared rule, of knowing whether the communication is intended for him or not. An advantage of the embodiments that have been described is that they allow simultaneous and symmetrical communication between a master and two slaves, even though these two slaves share the same address on the bus originally. This may be of interest for example in real-time processing applications, alarm management, etc. Another advantage is to allow communication between a master circuit and two slave circuits, without address constraint at the slave circuits. FIG. 8 is a timing diagram illustrating another example of a communication protocol to which the described embodiments can be applied. This is a single bus communication protocol in which the synchronization signal is transmitted together with the data (and, if applicable, the power signal). As in the previous embodiments, the bus (signal SW) is at rest in a high state VH.

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However, unlike the protocols described above, the bus modulation switches contained in the master and slave circuits do not pull the bus to ground, but at a level VL lower than the VH level. To transmit data, the circuit concerned modulates the signal SW in amplitude between the two levels VH and VL. In the example shown, a transmission initiated by the master circuit is initialized by a start bit START in which the signal SW is forced (time t5) at the level VL. This initializes the slave circuits and prepares them to receive data. The master circuit modulates the level of the signal SW at the rate of a clock signal which sets the transmission rate. The transmission of a bit at level 0 is effected, for example, with a VL level pulse having a duration less than the half-period of the clock signal (in the example represented, a quarter of the period T ) whereas a level 1 is coded with a pulse of level VL of duration greater than the half-period of this signal (for example three quarters of the period T). The slave circuits detect the amplitude variation and the corresponding duration of the high and low pulses to determine the value of the transmitted bits. A transmission end (usually the end of a frame) is encoded by the transmitter circuit in the form of a high state (bus release) for a duration greater than the period T.

The embodiments of the identification method which have been described above apply to such a communication bus to the extent that the transmission of a 0 also has priority over the bus with respect to the transmission of a message. state 1. An interpretation of the state of the bus allows the slave circuits to determine the order relation which binds their identifiers and which sets the order of the subsequent communications. Various embodiments have been described, various variations and modifications will be apparent to those skilled in the art. In particular, the embodiments which have been described B10602 - 10-RO-292

16 apply more generally to any serial communication bus in which the bus is, at rest, placed at a potential different from the ground, that this potential is positive or negative, provided that each bit is transmitted over an identical period whatever his condition. In addition, the practical implementation of the embodiments that have been described is within the abilities of those skilled in the art from the functional indications given above and by using the usual circuits equipping slave circuits. In the case where the circuits are equipped with programmable microcontrollers, the embodiments described can be implemented on existing systems that simply reprogram.

Claims (10)

REVENDICATIONS1. A method of communication between a master circuit (1, M) and two slave circuits (3, 3 '; S1, S2) on a serial bus (I2C; 44) in which: the two slave circuits transmit identifiers at the same time (UID1 , UID2) associated with them; the two slave circuits transmit at the same time the inverse (NUID1, NUID2) of these identifiers; and each slave circuit exploits the combinations present on the bus to determine a communication order between the two circuits. 2. Method according to claim 1, wherein the master circuit (1; M) triggers the preceding steps by sending a specific command (GET UID) on the bus. 3. The method according to claim 2, wherein said command (GET UID) is preceded by the sending by the master circuit (M) of an address (Slave address) common to both slave circuits (3, 3 '; S1, S2). 4. Method according to any one of claims 1 to 3, wherein each slave circuit (3, 3 '; S1, S2) 20 determines a relationship between its own identifier (UID1, UID2) and that of the other slave circuit . 5. The method of claim 4, wherein the relationship between the identifiers (UID1, UID2) is a relation of order. 25 6. Method according to any one of claims 1 to 5, wherein each slave circuit (3, 3 '; S1, S2) transmits, to the master circuit (1; M), an address (ADD1, ADD2) concerning it, the transmission order being fixed by the relation between the respective identifiers (UID1, UID2) of the slave circuits. 7. Method according to any one of claims 1 to 5, wherein each slave circuit (3, 3 '; S1, S2) transmits, to the master circuit (1; M), its identifier (UID1, UID2) as a Address.B10602 - 10-RO-292 18 The method of any preceding claim, wherein the bus is an open drain bus (or open collector) in which a bit is transmitted over a period of time independent of the state of the bit. 9. An electronic circuit (1, 3, 3 ', M, S1, S2) for transmission over a serial bus, comprising means suitable for carrying out the method according to any one of the preceding claims. 10. Master-slave transmission system between a master (1; M) and two slaves (3, 3 '; S1, S2), comprising circuits according to claim 9.