FR2962567A1 - METHOD FOR OPTIMIZING MEMORY ACCESS, WHEN RE-EXECUTING AN APPLICATION, IN A MICROPROCESSOR COMPRISING SEVERAL LOGICAL HEARTS AND COMPUTER PROGRAM USING SUCH A METHOD - Google Patents

Abstract

The invention particularly relates to the optimization of memory access, when the execution of a main application is resumed, in a microprocessor comprising several logical cores and allowing the simultaneous execution of at least two processes in an environment comprising a hierarchically organized shared memory comprising high and low portions, data being copied from the bottom to the high for processing by the application. The computer is adapted to interrupt the execution of the main application. During an interruption of the execution of this application, a reference to a data stored in an upper part of the memory is stored, this data to be used to allow the execution of the application. After programming a restart execution of the application and before its recovery, this data is accessed in a lower part of the memory according to the reference to be stored in a high part of the memory.

Description

The present invention relates to memory accesses in microprocessors and more particularly to a memory access optimization method, when the execution of an application is resumed, in a microprocessor comprising a plurality of logical cores, for example a microprocessor implementing a technology known as simultaneous multi-threading, especially in the context of high performance computing, and a computer program implementing such a method. High Performance Computing, also known as High Performance Computing (HPC), is developing for both academic research and industry, particularly in technical fields such as aeronautics, energy, climatology and the sciences of life. In particular, modeling and simulation make it possible to reduce development costs and speed up the launch of innovative, more reliable and less energy-consuming products. For researchers, high performance computing has become an indispensable means of investigation. These calculations are generally implemented on data processing systems called clusters. A cluster typically comprises a set of interconnected nodes. Some nodes are used to perform compute tasks (compute nodes), others to store data (storage nodes), and one or more others manage the cluster (administrative nodes). Each node is for example a server implementing an operating system such as Linux (Linux is a brand). The connection between the nodes is, for example, made using Ethernet or Infiniband links (Ethernet and Infiniband are trademarks).

Figure 1 schematically illustrates an example of a topology 100 of a cluster, type fat-tree. The latter comprises a set of generically referenced nodes 105. The nodes belonging to the set 110 are here computation nodes while the nodes of the set 115 are service nodes (storage nodes and administration nodes). The computing nodes can be grouped into subsets 120 called computing islands, the set 115 being called service island.

The nodes are connected to each other by switches (called switches in English terminology), for example hierarchically. In the example illustrated in FIG. 1, the nodes are connected to first level switches 125 which are themselves connected to second level switches 130 which are in turn connected to third level switches 135. As illustrated in FIG. 2, each node generally comprises one or more microprocessors, local memories as well as a communication interface. More specifically, the node 200 here comprises a communication bus 202 to which are connected: central processing units or microprocessors 204 (or CPU, acronym for Central Processing Unit in English terminology); components of RAM 206 (Random Access Memory in English) with registers adapted to record variables and parameters created and modified during the execution of programs (as illustrated, each memory component alive can be associated with a microprocessor); and, communication interfaces 208 adapted to transmit and receive data. In this case, the node 200 also has internal storage means 210, such as hard disks, which can in particular comprise the executable code of programs. The communication bus allows communication and interoperability between the various elements included in the node 200 or connected to it. The microprocessors 204 control and direct the execution of the instructions or portions of software code or programs. When powering up, the program or programs that are stored in a non-volatile memory, for example a hard disk, are transferred into the RAM 206.

To improve the performance of each node, the microprocessors used are often multi-core microprocessors, that is to say microprocessors comprising several cores that can be used in parallel.

Moreover, since the execution time of instructions in a microprocessor is generally shorter than the access time to data in memory, particular memories, called cache memories, are generally used. Thus, typically, there is a memory hierarchy according to which different memories are organized according to their access time and cost and, consequently, their size. Such an organization is represented in FIG. 3. The memory here comprises six types of memories arranged in a hierarchical manner: a mass memory, a central memory, an L3 level cache, a L2 level cache, a cache memory of level L1 and a register. As illustrated, the more the type of the memory is expensive and fast, the more the size of the corresponding memory is limited. A possible optimization of the execution of an application then consists in putting data back in the memory hierarchy during the execution of the application, from a low-level memory, for example a mass memory, to a memory. high-level cache, preferably a L1 cache, or a register, so that the data to be used is as close as possible to the microprocessor when the latter needs it. Such an optimization, known as prefetching in English terminology, may be explicit and carried out in the application itself by means of corresponding instructions. It can also be implicit and performed by a compiler when compiling the application or by the microprocessor itself when running the application. However, while this technology significantly improves the performance of a microprocessor, its implementation can be disrupted by the execution of ancillary programs. Indeed, during the execution of a main program, interruptions are often generated to execute, in particular, ancillary tasks of the operating system called daemons. Following an interrupt and during the execution of a daemon, caches are then optimized for the execution of this daemon. Therefore, after the execution of the daemon and when the microprocessor executes the main application again, the cache memories contain data relating to the daemon and there is a latency from the ascent, in the memory hierarchy, of related data. to the main application. The invention solves at least one of the problems discussed above.

The invention thus relates to a method for computer optimization of memory access in a microprocessor of said computer when resuming execution of a main application, said microprocessor allowing the simultaneous execution of at least two processes in an environment comprising a hierarchically organized shared memory comprising at least an upper part and a lower part, at least one piece of data being copied from the bottom part to the top part to be processed by said main application, said computer being adapted to interrupt the execution of said main application, this method comprising the following steps, - during an interruption of the execution of said main application, storing at least one reference to at least one data item stored in an upper part of said memory , said at least one datum to be used to enable the execution of said application p principal; after scheduling a resumption of execution of said main application and before resuming execution of said main application, accessing said at least one datum in a lower part of said memory according to said at least one reference; and storing said at least one datum in an upper part of said memory. The method according to the invention thus makes it possible, in anticipation, to access data to be processed by an application during its recovery, thus reducing the time for this recovery. The method preferably further comprises a step of accessing at least one configuration parameter of said main application, said step of accessing said at least one data being performed according to said at least one parameter. Advantageously, the method further comprises a preliminary declaration step during which said at least one main application is declared privileged and a step of defining said at least one parameter. Such a declaration makes it possible to trigger the memory access optimization process selectively according to the applications executed. According to a particular embodiment, the method further comprises a step of verifying said at least one parameter, said at least one parameter defining a data block size, said at least one reference comprising at least one memory address. The method thus makes it possible to avoid memory access errors. Still according to a particular embodiment, said processor allows the implementation of at least two logical cores, each of said at least two processes being able to be executed by a logical core, said at least two logical cores sharing said shared memory, said application principal being executed by one of said at least two logical cores, instructions relating to the execution of said steps of access and storage of said at least one data being transmitted to the other of said at least two logical cores. The method according to the invention thus makes it possible to optimize the access to data necessary for the resumption of execution of the main application without degrading the performance of the applications.

Said microprocessor is preferably a microprocessor mufti-cores, said at least two logical cores being implemented in the same physical core so that they share a large part of the memory hierarchy used to optimize access data and thus resume execution of a main application. According to a particular embodiment, said instructions for storing said at least one reference to said at least one datum and accessing said at least one datum are initiated by a logical layer of said computer, for example a layer of a system operating system implemented in said computer. The method according to the invention is thus easy to implement and requires only a few modifications. The invention also relates to a computer program comprising instructions adapted to the implementation of each of the steps of the method described above when said program is executed on a computer and a means of storing information, removable or no, partially or completely readable by a computer or a microprocessor comprising code instructions of a computer program for the execution of each of the steps of the method described above. The benefits provided by this computer program and storage means are similar to those mentioned above. Other advantages, aims and features of the present invention will become apparent from the detailed description which follows, given by way of non-limiting example, with reference to the appended drawings, in which: FIG. 1 illustrates an example of a topology of a cluster; FIG. 2 illustrates an exemplary architecture of a node of a cluster; FIG. 3 schematically represents the hierarchical organization of memories in a data processing system; FIG. 4, comprising FIGS. 4a and 4b, illustrates the general concept of the invention according to which data are preloaded in advance; FIG. 5 illustrates an example of instruction sequences in a processor core comprising two logical cores embodying the invention; FIG. 6, comprising FIGS. 6a to 6d, represents extracts from the contents of a level L1 cache memory of the microprocessor core described with reference to FIG. 5, at different times; FIG. 7, comprising FIGS. 7a and 7b, schematically illustrates certain steps of an exemplary algorithm implemented in an operating system to offer a memory feeding function to a main application; FIG. 8 illustrates certain steps of an exemplary algorithm implemented by a memory load son process making it possible to optimize the execution restart of a main application; and FIG. 9 is a simplified representation of the logic architecture of a microprocessor of a node belonging to a cluster, the microprocessor here comprising two cores each implementing two logical cores. In general, the invention aims at a mechanism for prefetching cache memory to load data related to the execution of a first application, during the execution of a second application executed following an interruption of execution. of the first application, to allow an optimal execution of the first application. It is recalled here that some microprocessors include several logical cores. When these microprocessors comprise several physical cores, each of them is generally adapted to implement several logical cores. This technology, called, in English terminology, simultaneous multi-threading (or hyperthreading according to the Intel implementation, Intel is a trademark), allows several elementary processes (called threads in English terminology) to be run in parallel in a physical core of a microprocessor. A physical heart implementing this technology is thus generally perceived as a double-core by the logical layer exploiting the physical heart. A physical heart implementing this technology includes shared resources between logical cores and resources specific to each logical core. Shared resources are typically threads, cache memories, and bus interfaces. The own resources include the registers of data and instructions of the logical core, segments and control as well as the interrupt controller (called APIC, acronym of Advanced Programmable Interrupt Controller in English terminology).

However, while this technology can significantly improve the performance of a microprocessor for particular applications, including image processing applications, it has been observed that these performances were only slightly improved, or degraded, for a particular purpose. other applications, including scientific computing applications.

It is therefore generally disabled in clusters used for high performance computing. Nevertheless, this technology allows the execution of a small number of instructions by a logical core without disturbing the execution of another application executed by another logical core, the invention uses it to allow the anticipated loading of a cache memory when an add-on application is running. Thus, at a given moment, a first logical heart is associated with the execution of the auxiliary application while a second logical core is used to load a cache memory with data relating to a main application (ie say a privileged application), in advance. Thus, according to the invention, a first process, for example an HPC type application process, is assisted by a second process, called a child process, whose function is to bring back in cache memory the data necessary for the execution of the first process. process after it has been interrupted. The data is brought back in advance to optimize the resumption of the execution of the first process. These processes are advantageously implemented in two logical cores of a physical core to optimize the execution performance of the first process without increasing the costs associated with the hardware components used. Such a mechanism, which can be considered as a transition prefetching, is here called memory feeding.

Figure 4, including Figures 4a and 4b, illustrates the general concept of the invention. More precisely, FIG. 4a shows a sequence diagram during the resumption of execution of a task in a microprocessor allowing the implementation of two logical cores whose logical core is not used whereas FIG. sequence diagram when resuming execution of a task in this same microprocessor when the two logical cores are used to implement the invention. The processor used to execute a main application here comprises a physical core 400 implementing two logic cores 405-1 and 405-2. The lines placed to the right of the heart 400 represent, temporally, the tasks performed by each of the logical cores. The reference 410 here designates the depth of the memory hierarchy. The lower part represents the lower part of the hierarchy, ie the low-level memory (the most distant memory of the microprocessor), while the upper part represents the upper part of the hierarchy, that is to say ie the high-level memory (the closest memory to the microprocessor). Thus, in order to process data that is not present in a high-level memory, an access instruction to this datum must go down to find it in a lower-level memory and then raise it. As illustrated in FIG. 4a, when the logic core 405-2 is not used, the logic core 405-1 performs all the tasks. It is admitted here that the execution of the main application is interrupted at a given moment (not shown) to execute an auxiliary application which includes, for example, the task 415. During the execution of this task, the cache memories containing main application data are discarded in favor of application-related data. Thus, when resuming the execution of the main application, at the time referenced 420, the task 425 of the main application is suspended during a period referenced 430 corresponding to the access time to the data necessary for the execution of the task. The access time to these data is here materialized by the arrow (downward and upward) crossing the depth of the memory hierarchy. As indicated by reference 425 ', execution of the main application resumes as soon as the data is available. If the data sought are generally no longer in the memory closest to the microprocessor, they are also not systematically in the most distant memory. Thus, the period 430 has a variable duration related to the position of the searched data in the memory hierarchy. When two logical cores of a physical core are used to implement the invention, one of the logical cores, for example the logical core 405-1, is used to execute the main application as well as the associated applications, in particular the demons, while the other logical heart, here the 405-2 logical core, is used to execute an application related to the main application and allowing a transition prefetching. As illustrated in FIG. 4b, a task 415 of an additional application can be executed by the logic core 405-1 following the interruption of the execution of the main program. At the same time, the logic core 405-2 is used to load in a memory close to the microprocessor, typically a L1 cache, data that will be needed to execute the main application when it is resumed. This data access task allowing the resumption of the execution of the main application is here referenced 435. Thus, when resuming the execution of the main application, referenced 440, the data necessary for its execution are present in a memory near the microprocessor which can then perform a task 445 of the main application without waiting for the availability of data. The access time to this data, referenced 130 ', is a time masked by the execution of ancillary applications. It does not affect the execution of the main application. It is observed here that the mode of cooperation between a main application executed by a logical core and a secondary application, executed by a second logical core, for the purpose of loading data relating to this main application, may be strict or loose. When the mode of cooperation is strict, an explicit synchronization between the applications is necessary whereas if it is cowardly, these applications are executed independently of one another, the secondary application of data loading being able to know the needs in terms of memory of the main application. Memory references are advantageously used to allow the secondary application to anticipate the memory accesses of the main application in order to shorten the corresponding memory access time when resuming its execution. The memory map can be obtained from a static analysis made from data from the compilation of the main application. This mapping makes it possible to designate blocks of memories which, associated with a division of time, make it possible to anticipate the memory accesses of the main application. The cartography can also be dynamic, deduced from reading memory context traces left by the application itself, by the code of the context switch of the hardware operating system or via inter-process mechanisms. FIG. 5 illustrates an example of instruction sequences in a processor core comprising two logical cores embodying the invention. FIG. 6, described in parallel with FIG. 5 and comprising FIGS. 6a to 6d, represents extracts from the contents of a level L1 cache memory of the microprocessor core described with reference to FIG. 5, at different times. In Fig. 5, references 500-1 and 500-2 denote instruction sequences of a first and a second instruction engine corresponding to first and second logic cores, respectively. The first statement engine is used to run multiple applications including a main HPC compute application and related operating system tasks. The second instruction engine is dedicated to the execution of a secondary application for loading data related to a main application executed by the first instruction engine, here an HPC calculation application. Between times t1 and t1, the instructions executed by the logic core corresponding to the sequence of instructions 500-1 are instructions from the main HPC calculation application, referenced 505-1. Between times t1 and t2, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of an operating system task, referenced 510-1.

At time t1, a prefetching mechanism is implemented, as a standard, for pre-loading data relating to instructions 510-1 in order to optimize the execution of these instructions. The level L1 cache memory of the microprocessor core then essentially comprises data relating to the main HPC calculation application previously executed as well as some data relating to the executed task of the operating system, as illustrated in FIG. 6a. In addition, the HPC main calculation application being referenced as a privileged application, the execution context is stored when the execution of this application is interrupted. In other words, the addresses of the data present in the cache memory are stored for later loading, before resuming the execution of this main application. Between instants t2 and t3, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of a first application attached, referenced 515. Similarly, between instants t3 and t4, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of the aforementioned operating system task, referenced 510-2. Similarly, between times t4 and t5, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of a second subsidiary application, referenced 520. Between times t5 and t6, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of the aforementioned operating system task, referenced 510-3. Similarly, between times t6 and t7, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of a third subsidiary application, referenced 525. The cache L1 level of the heart of the The microprocessor then comprises data relating to the task of the operating system executed as well as to the first, second and third subsidiary applications, as illustrated in FIG. 6b. Between times t0 and t7, the logic core corresponding to the sequence of instructions 500-2 does not execute any instructions. At time t7, the memory feeding mechanism, allowing the anticipated loading of data relating to a main application before resuming its execution is implemented. At this time, the logical heart corresponding to the sequence of instructions 500-2 then executes instructions, referenced 530, to cache the data whose addresses were stored during the interruption of the main program. Thus, between times t7 and t8, the instructions executed by the logical heart corresponding to the sequence of instructions 500-1 are instructions of the aforementioned operating system task, referenced 510-4, while the instructions executed by the logical heart corresponding to the sequence of instructions 500-2 are instructions allowing the cached loading of the data whose addresses were stored during the interruption of the main program.

At time t8, the memory cache L1 level of the core of the microprocessor then includes data relating to the task of the operating system executed, the second and third additional applications, that is to say, data relating to the last instructions executed, as well as data relating to the main application and allowing an optimal recovery of the execution of the latter, as illustrated in Figure 6c. The execution of the main program is resumed at this moment as illustrated by reference 505-2. Still from that moment, the logical heart corresponding to the sequence of instructions 500-2 no longer executes instructions. As illustrated in FIG. 6d, the level memory cache L1 of the microprocessor core comprises, at time t9, essentially data relating to the main HPC calculation application as well as some data relating to the task of the operating system previously executed that have not yet been replaced by data relating to the HPC main calculation application. Thus, the main application running on one of the logical cores is aided by a child process running on another logical heart of the same physical heart. This child process assumes the task of retrieving the data needed for the main application in advance to save waiting cycles that the main application should undergo while waiting for the requested data. In other words, the object of the invention is in particular to set up a cooperative mechanism between the operating system used and a memory loading process executed by a logical core belonging to a physical core of which another logical core executes a main application, the logical cores sharing at least part of the memory hierarchy.

Thus, typically, the operating system launches on a specified logical heart a child process for implementing a memory feeding function when called or solicited. This child process can only be used for applications considered to be main, ie, for example, declared with a particular privilege. It is observed that when an application has been declared with such a privilege, the operating system makes the necessary checks in terms of privilege and setting. If, after verification, the authorization is given, the main application can access the memory feeding function when it is interrupted in its execution.

When the main application is interrupted, the operating system stores markers on the memory areas used by this application before its interruption. After these pins have been stored, the operating system can elect a new non-privileged task which is then executed by the logical core executing the main application. Such markers are, for example, pairs of addresses and lengths specifying sets of data.

When the operating system determines the resumption of execution of the main application via its scheduler, it controls the function of memory feeding with the child process. The latter then triggers the readings from the memory area references that the operating system has retained. It will thus shorten the memory distance and save waiting cycles with each restart of the context switch. Advantageously, a main application can control the call to the memory feeding function by enabling or disabling the service to the operating system. Of course, the main application and the child process must be executed in environments in which at least part of the memory hierarchy is shared. The main application and the child process are thus preferably executed by two logical cores of the same physical heart. The OpenCL standard can be used to implement the interface described above between a main application and a memory loading son process allowing the use of the memory feeding function. The functions used in such an interface are, for example, the following: - a function to return the memory feeding capabilities of the operating system used to an application, and int clMFeedQuery (and MFeed * mf) where mf represents the parameter of the function whose type is and MFeed; - a function allowing an application to declare itself as a privileged application to the operating system in order to benefit from the memory feeding function, and int clMFeedDeclare (and MFeed mf, and MFeedParams * mfparams) where mf represents the parameter of the function whose type is and MFeed and mfparams represents the parameter of the function whose type is and MFeedParams; Advantageously, this function modifies the parameterization of the application, particularly in terms of the size of data blocks to prefetcher and synchronization with the child process to perform the memory feeding. These parameters are important and should preferably be checked because a wrong parameterization has the effect of accentuating the pollution effects for the other processes performed; and, - an activation function and a function of deactivating the service of memory feeding, and int clMFeedStart (and MFeed * mf) and int clMFeedStop (and MFeed * mf) where mf represents the parameter of the function whose type is and MFeed. FIG. 7, comprising FIGS. 7a and 7b, schematically illustrates certain steps of an exemplary algorithm implemented in an operating system for providing a memory feeding function to a main application. Figure 7a is essentially the phase related to the interruption of the execution of a main application while Figure 7b relates to its recovery. It is admitted here that the main application has previously declared itself as privileged and that the operating system has controlled its 25 parameters of memory feeding. A first step (step 700) is to detect an interruption. If an interrupt is detected, a next step (step 705) consists of a test to determine whether the interrupt is for suspending the execution of a main application or not.

If the interrupt aims to suspend the execution of a main application, the context of the execution of this application is stored (step 710). As indicated above, this step notably makes it possible to store memory references during the main application. Otherwise, if the interrupt is not aimed at suspending the execution of a main application, the interruption is processed in a standard way (step 715). As long as it is not stopped, this algorithm is repeated to process all interrupts. At the same time, as illustrated in FIG. 7b, when the resumption of the execution of a process is scheduled by the scheduler (step 720), a test is performed to determine whether the application corresponding to the process whose restart is programmed is a main application or not (step 725). If the application corresponding to the process whose resumption is programmed is a main application, the memory loading son process is called to implement a memory feeding function (step 730). This step aims to remount in the memory hierarchy, data whose references were stored during the storage of the execution context of the main application according to the parameters of the latter (set at the time of the declaration of the application as the main application). It is recalled here that the child process is preferably executed by a logical heart belonging to a physical heart comprising another logical heart used to execute the main application so that the child process and the main application share at least part of the memory hierarchy. Its purpose is to retrieve data from previously memorized addresses according to block sizes related to the main application. As long as it is not stopped, this algorithm repeats itself to handle all application runtimes. FIG. 8 illustrates certain steps of an exemplary algorithm implemented by a memory load son process making it possible to optimize the execution of a main application. After being called, the memory loading son process accesses (step 800) references previously stored during the interruption of the execution of the main application and the parameters related to this application. The stored references include in particular data addresses while the parameters include, in particular, data block sizes to prefetcher as well as synchronization information. As described above, due to the execution of separate processes of the main application, the data to be used by the main application is generally no longer stored near the microprocessor, that is to say in an upper part of the memory hierarchy, in particular in the L1 cache, but in a lower part. The references accessed are therefore used to access, according to a standard mechanism, these data (step 805) which are in the memory hierarchy. According to this mechanism, a test is performed on a first level of memory, for example an L1 cache, to determine if the data are present at this level. If so, they are accessed according to predetermined parameters. If not, another test is performed on a second memory level, lower than the first memory level, for example a L2 cache, to determine if the data is present at this level. Thus, by testing the presence of the data sought in each memory level, step by step, the data are found in the highest memory level. The accessed data is then stored in a high part of the memory according to predetermined parameters (step 810). It is observed here that, as suggested by the use of dashed line, this step is generally not implemented explicitly by the child process. Indeed, this step results from the access to the data. It is automatically performed by the microprocessor during access through the cascading effects of hardware calls. As indicated above, many microprocessors that can be used in cluster nodes implement the technology called simultaneous multi-threading (or hyperthreading according to the Intel implementation, Intel is a trademark) to create logical cores. When using these microprocessors, this technology can be activated or not. FIG. 9 schematically represents the logical architecture of a microprocessor of a node belonging to a cluster, the microprocessor here comprising two physical cores each implementing two logical cores, that is to say a microprocessor in which the simultaneous multithreading has been enabled, when a high performance computing application is running. Each physical heart allows here to execute up to four instructions in the same cycle because of the different execution units implemented in each physical heart. Thus, two logical cores can each execute up to four instructions depending on the use made by the other heart. As illustrated, the physical cores 900-1 and 900-2 are connected to a system bus 905 to which can be connected in particular a communication interface and a memory. Each physical core includes threads shared between logical cores and an instruction register specific to each logical heart. Thus, the physical heart 900-1 comprises a set 910-1 of execution units as well as the instruction register 915-11 linked to a first logical heart of the physical heart 900-1 and the instruction register 915- 12 linked to a second logical heart of the 900-1 physical heart. Similarly, the 900-2 physical core includes a set 910-2 of execution units as well as the instruction register 915-21 linked to a first logical core of the 900-2 physical heart and the instruction register 915. -22 linked to a second logical heart of the 900-2 physical heart. The instructions executed by each of the logical cores are here represented by the black squares. Thus, as illustrated, the logical cores associated with the instruction registers 915-11 and 915-21 are in charge of executing all the applications as well as the operating system, with the exception of memory management thread processes which are performed by the logical cores associated with memory registers 915-21 and 915-22 to allow fast recovery of the main applications executed by logical cores associated with instruction registers 915-11 and 915-21. Naturally, to meet specific needs, a person skilled in the field of the invention may apply modifications in the foregoing description.

Claims (10)

REVENDICATIONS1. A computer method for optimizing memory access in a microprocessor of said computer when resuming execution of a main application, said microprocessor enabling the simultaneous execution of at least two processes in an environment comprising an organized shared memory of a hierarchical manner comprising at least one upper part and one lower part, at least one piece of data being copied from the lower part to the top part to be processed by said main application, said computer being adapted to interrupt the execution of said main application, this method being characterized in that it comprises the following steps, - during an interruption of the execution of said main application, o storage (710) of at least one reference to at least one data item stored in an upper part of said memory, said at least one datum to be used to allow execution of said applicatio n main; after programming a resumption of execution of said main application and before resuming execution of said main application, access (805) to said at least one datum in a lower portion of said memory according to said at least one reference; and storing (810) said at least one datum in an upper portion of said memory. 2. Method according to the preceding claim further comprising a step of accessing (800) at least one configuration parameter of said main application, said step of accessing said at least one data being performed according to said at least one parameter. 3. Method according to the preceding claim further comprising a preliminary declaration step during which said at least one main application is declared privileged and a step of defining said at least one parameter. 4. Method according to the preceding claim further comprising a step of verifying said at least one parameter, said at least one parameter defining a data block size, said at least one reference comprising at least one memory address. 5. Method according to any one of the preceding claims wherein said processor allows the implementation of at least two logical cores, each of said at least two processes can be executed by a logical core, said at least two logical cores sharing said shared memory, said main application being executed by one of said at least two logical cores, instructions relating to the execution of said steps of access and storage of said at least one datum being transmitted to the other of said at least two logical hearts. 6. Method according to the preceding claim wherein said microprocessor is a multi-core microprocessor, said at least two logical cores being implemented in the same physical core. 7. Method according to any one of the preceding claims, wherein said instructions for storing said at least one reference to said at least one datum and accessing said at least one datum are initiated by a logical layer of said computer. 8. Method according to the preceding claim wherein said logic layer belongs to an operating system implemented in said computer. 9. Computer program comprising instructions adapted to the implementation of each of the steps of the method according to any one of the preceding claims when said program is run on a computer. 10. An information storage medium, removable or not, partially or completely readable by a computer or a microprocessor comprising code instructions of a computer program for the execution of each of the steps of the method according to any one of the Claims 1 to 8.