FR2953310A1 - OPERATOR ADDITION / SUBTRACTION EQUIPMENT, PROCESSOR AND TELECOMMUNICATION TERMINAL INCLUDING SUCH AN OPERATOR - Google Patents

Abstract

This hardware add / subtract operator (72) has a plurality of hardware add / subtract modules (74, 76, 78) and a plurality of data links between these modules, on the one hand, and inputs (E1, E2, E3, E4, E5, E6) and outputs (S1, S2, S3) of the operator and these modules, on the other hand, according to a predetermined structure for carrying out arithmetic calculations. At least a portion (74, 76, 78) of the operator addition / subtraction hardware modules and at least a portion (80, 82, 84, 86) of links between these modules are configurable using at least one programmable parameter (α1, a2, a3, a4, β1, β2, β3), at least between a first configuration in which the operator (72) finalizes a calculation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a calculation of imaginary portions of fast Fourier transform coefficients, and a third configuration in which the operator performs a computation of path and survivor metric values of an implementation of the algorithm from Viterbi.

Description

The present invention relates to a material operator of additions / subtractions of predetermined structure for carrying out arithmetic calculations with the aid of material modules of addition and / or subtraction. It also relates to a processor and a telecommunication terminal including this hardware operator. A large number of telecommunication terminals, in particular the multi-carrier modulation / demodulation terminals of the transmitted / received and channel decoded signals, comprise digital processing components generally and advantageously involving FFT digital direct signal calculations. (of the English "Fast Fourier Transform") or inverse fast Fourier transform known as IFFT (of the English "Inverse Fast Fourier Transform"), and an implementation of the algorithm of Viterbi, in particular within the framework of the radio Software or Reconfigurable Radio SDR (Software Defined Radio). However, the FFT / IFFT calculation and the implementation of the Viterbi algorithm require, among other things, specific addition / subtraction operations. An SDR transmission / reception terminal is a terminal in which the digital / analogue conversion is closer to the antenna, so that the modulation / demodulation and coding / decoding processes executed by the terminal are carried out. on digital signals. These digital signals are indeed better suited to a reconfigurable treatment, that is to say capable of adapting to different standards or different evolutions. Unfortunately, the performances and the excessive consumption of the processors do not make it possible to envisage a purely software implementation of the digital processes and it is then necessary to resort to an implementation at least partially material.

In this context, hardware add / subtract operators find their utility in the aforementioned telecommunication terminals, at least for the FFT / IFFT and Viterbi calculations, in order to guarantee real-time operation. These add / subtract material operators, after having been specifically designed for this or that application, can be included in FFT / IFFT processors, in processors implementing the Viterbi algorithm, or in any other processor executing a processing involving arithmetic calculations using hardware add-on and / or subtract modules.

However, the proliferation of standards, and in particular wireless communication standards, requires the provision of terminals capable of managing different standards. A first solution to manage several standards is to juxtapose within the same terminal the different processing chains of standards considered each with their hardware operators. This solution is simple to implement but has the major disadvantage of not being effective in terms of the silicon surface used, that is to say in terms of hardware operators used.

Another solution is to design the different processing chains so that they share some of their functional modules and hardware operators. This second solution provides for a parameterization of the terminal so that its reconfiguration so that it executes such or such chain of treatment requires only a change of parameter values. Notably, a technique of pooling material operators is presented in the article by L. Alaus et al, entitled "Promising technique of parametrization for reconfigurable radio, the Common Operators Technique: fundamentals and examples", published in Journal of Signal Processing Systems, DOI 10.1007 / s11265-009-0353-04, March 14, 2009.

By way of example, this article indicates that a hardware operator of FFT / IFFT calculation can be advantageously pooled because it is solicited by a large number of standards. Indeed, most current or in preparation telecommunication standards are based on OFDM (Orthogonal Frequency Division Multiplexing) modulations. OFDM modulation is a method of coding orthogonal frequency division digital signals. The principle of OFDM modulation consists of multiplexing a communication by distributing it over sub-channels sent simultaneously on independent frequencies. The very heart of an OFDM modulation involves an FFT calculation.

The FFT operator is more generally involved as a basic operator of signal reception functions in the frequency domain. For example, an FFT operator is used in a frequency implementation of an equalization channel estimation, in a multi-carrier modulation / demodulation and in the execution of a so-called "channelization" function (ie channel selection) on a bench filters. This operator can therefore be used at different levels of a processing chain and in the context of different standards. It makes it possible to envisage obtaining a reconfigurable terminal presenting a limited number of hardware operators for calculating FFT. However, this solution now has its limits because, even within an operator or FFT calculation processor, several operators of additions / subtractions of different structures must be used. For example, the addition / subtraction operations involved in the calculation of real parts of FFT coefficients are not the same as the addition / subtraction operations involved in the calculation of the imaginary parts.

In addition, between an operator or FFT calculation processor and an operator or implementation processor of the Viterbi algorithm, the addition / subtraction operations involved are also different and justify providing separate hardware modules. It may then be desired to provide a hardware operator of additions / subtractions which makes it possible to at least partially solve the aforementioned problems and constraints and / or to improve the reconfigurability of a terminal. The subject of the invention is therefore a hardware add / subtract operator comprising a plurality of hardware add / subtract modules and a plurality of data transmission links between these modules, on the one hand, and between inputs and outputs of the operator and these modules, on the other hand, according to a predetermined structure for carrying out arithmetic calculations, in which at least part of the add / subtract material modules and at least part of the links between these modules are configurable to using at least one programmable parameter, at least between a first configuration in which the operator finalizes a calculation of real parts of fast Fourier transform coefficients, a second configuration in which the operator finalizes a calculation of imaginary parts fast Fourier transform coefficients, and a third configuration in which the operator performs a calculation of values of of paths and survivors of an implementation of the Viterbi algorithm.

Indeed, by parameterizing the addition / subtraction modules, the links between them and / or the links between these modules and the inputs / outputs of the hardware operator of additions / subtractions, it becomes conceivable to design a single hardware operator of predetermined structure capable, according to its configuration, of participating in different arithmetic operations including different phases of an FFT calculation and calculation of path and survivor metric values of an implementation of the Viterbi algorithm. The same generic hardware operator can therefore be requested by several functions, within the same treatment, for different treatments according to a common standard or even for different treatments according to different standards.

By ensuring that these processes include at least one FFT / IFFT calculation and an implementation of the Viterbi algorithm, this generic hardware operator is made particularly interesting for telecommunication applications, because it thus makes it possible to reduce the number of components. implanted in a terminal, in particular a multi-standard mobile terminal. The modulation / demodulation and channel coding / decoding functions can indeed be fulfilled in the same terminal on the basis of one or more common generic hardware operators, thereby limiting the number and size of the hardware elements to be integrated into the network. terminal. In addition, the calculations of real parts and imaginary parts of FFT coefficients taking place on complex data, the generic operator obtained, configurable between such calculations and a computation of values of path and survivor metrics of an implementation. of the Viterbi algorithm, is able to process input data either hard (binary) or flexible (encoded on several bits) to perform Viterbi decoding.

Optionally, the addition / subtraction hardware modules and the configurable links are furthermore configurable using said at least one programmable parameter, in a fourth configuration in which the operator performs several addition and / or independent subtraction and a fifth configuration in which the operator finalizes a cascade of addition and / or subtraction operations. Optionally also, a hardware add / subtract operator according to the invention may comprise a first hardware module for addition / subtraction that can be configured, using a first binary parameter, between an adder configuration and a configuration. subtractor, a second configurable addition / subtraction hardware module, using a second binary parameter, between an adder configuration and a subtractor configuration, and a third configurable add / subtract hardware module, using a third binary parameter, between an adder configuration and a subtractor configuration.

Optionally also, a hardware add / subtract operator according to the invention may comprise: a first link providing an operand value to the first configurable module, using a first multiplexing parameter, between a configuration for providing an input data of the operator and a configuration for supplying the output of the second configurable module, a second link for providing a first operand value to the second configurable module, using of a second multiplexing parameter, between a configuration for supplying an input data of the operator and a configuration for supplying the output of the first configurable module, a third connection for supplying a second operand value to the second configurable module, using a third multiplexing parameter, between an input data provisioning configuration of the operator and a provisioning configuration of the of the third configurable module, and a fourth link providing an operand value to the third configurable module, using a fourth multiplexing parameter, between a configuration for providing an input data of the operator and a configuration for providing the output of the second configurable module. Also optionally, each configurable link comprises a two-input multiplexer and an output and selection of one of the two inputs using a binary parameter.

The subject of the invention is also a digital data processing processor comprising at least one butterfly operator including at least one hardware add / subtract operator as defined above, the butterfly operator being configurable, using said programmable parameter between a first configuration in which it performs a fast Fourier transform calculation and a second configuration in which it performs a calculation of branch metric values and path and survivor metric values of an implementation of the algorithm from Viterbi. Optionally, a digital data processing processor according to the invention may comprise a plurality of configurable butterfly operators between said first configuration in which each throttle operator performs said fast Fourier transform calculation and said second configuration in which each throttle operator performs computation of branch metric values and path and survivor metric values of an implementation of the Viterbi algorithm, these butterfly operators being structured together for fast Fourier transform computation by an algorithmic approach of Cooley-Tukey in lattice type Radix-2 and for an implementation of the lattice Viterbi algorithm with four reference symbols. The subject of the invention is also a telecommunication terminal with multi-carrier modulation / demodulation of the transmitted / received signals and the decoding of signals processed by a convolutional code, comprising at least one hardware add / subtract operator as defined above. Optionally, a telecommunication terminal according to the invention can be modulating and demodulating OFDM type. Optionally also, a telecommunication terminal according to the invention may comprise at least one modulator / demodulator with modulation and demodulation OFDM compatible with each implemented standard and at least one signal decoder encoded by a convolutional code compatible with each implemented standard. The invention will be better understood with the aid of the description which follows, given solely by way of example and with reference to the appended drawings, in which: FIG. 1 schematically represents the general structure of a data processing network; lattice data for the implementation of an FFT / I FFT calculation, - Figure 2 schematically shows the structure of a throttle operator used by the data processing network of Figure 1, Figure 3 shows schematically the possible implementation in addition / subtraction and multiplication modules of the butterfly operator of FIG. 2, FIG. 4 schematically represents the general structure of a data processing chain for an implementation of the Viterbi algorithm, FIG. 5 schematically represents the structure of a throttle operator used by a part of the data processing chain of FIG. 4, FIG. the possible implementation in addition / subtraction modules of the butterfly operator of FIG. 5, FIG. 7 schematically represents the general structure of a material add / subtract operator according to one embodiment of the invention, usable in a throttle operator according to FIG. 3 or 6, FIGS. 8 to 11 represent the material additions / subtractions operator of FIG. 7 according to various possible configurations, and FIG. 12 schematically represents the general structure of a terminal of FIG. telecommunication according to one embodiment of the invention. The Fast Fourier Transform FFT is an algorithm for calculating the discrete Fourier transform. This algorithm is used in digital signal processing to transform discrete data of the time or space domain into the frequency domain.

For example, let N be the discrete time value x [0], ..., x [N-1] of a signal x. The N frequency values of the discrete Fourier transform X of this signal x are defined by the following formula: N1 X [k] = x [n] .wkn, for k = 0, ..., N-1, where w = e N n = 0 Since the inverse discrete Fourier transform is equivalent to the direct discrete Fourier transform, at a sign and factor 1 / N close, the fast IFFT inverse Fourier transform is based on the same algorithm as the FFT to compute this. inverse discrete Fourier transform. Any hardware operator or digital data processing processor configured for executing a FFT forward fast Fourier Transform calculation is therefore also suitable for calculating an IFFT inverse fast Fourier transform. A particularly simple and widely used implementation of the FFT calculation is the Cooley-Tukey algorithmic approach in Radix 2 subdivision. It assumes that the number N of transformed samples is a power of two and recursively subdivides the processing of n samples in two identical treatments of size n / 2 on a smaller scale. In fact, on a first scale: ## EQU1 ## where ## EQU1 ## where ## EQU1 ## where ## EQU1 ## [2n + lie N, n = 0 n = 0 2z nk ûi2? Ak N / 2û1 2z nk N / 2 + e N 1 x [2n + 1] .e N / 2 n = 0 Recurrently, a calculation of FFT at a given scale is achieved by two FFT calculations at a lower scale, one dealing with even samples, the other on odd samples of signal at the given scale.

With the aid of well-known additional simplifications, a trellis treatment is obtained at several scales (or levels) involving as many successive steps, as illustrated in FIG. 1 for N = 8 involving three steps St1. St2 and St3. Each step comprises N / 2 butterfly calculations, for a total number of N / 2 x log2 (N) butterfly calculations, such as that illustrated in FIG. 2. This butterfly calculation requires the cross computation of two data yk [0 ] and yk [1], comprising a complex multiplication of one of the data, yk [1], by a factor W to provide an intermediate value, and then a complex addition and subtraction between yk [0] and this intermediate value for provide two data yk + 1 [0] and yk + 1 [1]. In the example illustrated in FIG. 1, the factor W is w ° at the scale / step St1, w ° or w2 at the scale / step St2 and w °, w1, w2 or w3 at the scale / step St3. The two relations linking yk + 1 [0] and yk + 1 [1] to yk [0] and yk [1] take the following form: Yk + l Pl = Yk [o] + W'Yk [1], Yk In practice, the butterfly calculation is carried out by an operator structured in a first complex multiplication stage and a second stage of complex addition and subtraction receiving in the following manner: [...] input the output data of the first floor. To carry out its complex multiplication, the first stage comprises real multiplication hardware modules, hardware modules of actual addition / subtraction and data transmission links between these modules. In order to achieve complex addition and subtraction, the second stage comprises hardware modules of actual addition / subtraction and data transmission links to these modules. More precisely, noting: N / 2û1 X [k] = x [2n]. n = 0 N / 2û1 2, r nk N / 2û1 2, r nk X [k] = x [2n] .e Nl2 + Wk 1 x [2n + 1] .e Nl2 n = 0 n = 0 yk [1 ] = a + ib, W = c + id, yk [0] = e + lf, where a, b, c, d, e and f are real values, the need for material multiplication modules, addition and real subtraction: yk + ~ [0] = (ub + e) + i (bc + ad + f), yk + ~ [1] = (u + bd + e) + i (ubc + ad + f).

In this form, the calculation carried out by a throttle operator requires four real multiplication hardware modules, three actual addition hardware modules and three real subtraction hardware modules, as shown in FIG. 3. Specifically, the first stage of complex multiplication of the butterfly operator 10 shown in Figure 3, bearing the reference 12, comprises four multiplication modules 14, 16, 18 and 20 to respectively produce the products ac, bd, bc and ad, a subtraction module 22 receiving the output data of the modules 14 and 16 to perform the subtraction ac û bd and an addition module 24 receiving the output data of the modules 18 and 20 to achieve the addition bc + ad.

The complex addition and subtraction second stage of the throttle operator 10, bearing the reference 26, comprises: an addition module 28 receiving the output data of the module 22 and the variable e to perform the operation ac û bd + e, thus providing the real part denoted FFt-Re0 of yk +, [0], a subtraction module 30 receiving the output data of the module 22 and the variable e to perform the operation -ac + bd + e, thus providing the real part denoted FFt-Rel of yk + 1 [1], an addition module 32 receiving the output data of the module 24 and the variable f to perform the operation bc + ad + f, thus providing the imaginary part denoted FFt -Im0 of yk +, [0], and a subtraction module 34 receiving the output data of the module 24 and the variable f to perform the operation -bc - ad + f, thereby providing the imaginary part denoted FFt-Im1 of yk 1 [1]. It is then noted that the three addition and subtraction modules 22, 28 and 30 interconnected together constitute a first material additions / subtractions operator 36 and that the three addition and subtraction modules 24, 32 and 34 interconnected between they constitute a second material operator of additions / subtractions 38 of similar structure. The structures of these two material add / subtract operators 36 and 38, although having similarities, differ in that the first operator 36 has two subtractors (22, 30) and an adder (28), while the second operator 38 has two adders (24, 32) and a subtractor (34). In other conceivable forms, the calculation carried out by an FFT throttle operator may involve a slightly different structure, but this generally comprises at least the hardware operators 36 and 38 with three interconnected addition / subtraction modules. The general structure of a data processing chain for an implementation of the Viterbi algorithm is shown in Figure 4. This algorithm aims to find by recurrence the most likely sequence of states that produced a measured sequence [ X0, ..., XN_1] in the case of a signal encoded by a convolutional encoder, i.e. an encoder having a shift register in which each incoming bit generates an offset in the register and a result in exit. Its principle is to compare each value received with all the possible outputs of the shift register so as to determine what was the shift of this most probable register which generated the value received. The knowledge of this shift allows to know the value that caused it and therefore the generating value of the received message. For each received message value, a lattice structure is obtained, plotting the set of possible states of the shift register as ordinates and the set of possible transitions as the lattice pattern invariably repeating over time at each new entry. of the encoder. At the output of the encoder, only certain binary sequences are possible. They correspond to the different paths that exist in the lattice diagram. The application of the Viterbi algorithm then consists in finding, in the lattice, the binary sequence closest to the received sequence. In practice, the progress of the algorithm comprises the following three operations, at each instant and for each state of the trellis: a computation of values of branch metrics made by a block 40, consisting of calculating on receipt of N symbols ( for a yield of 1 / N) values representing the likelihood of the received symbols with respect to the 2N possible symbols. These 2N values are called the branch metrics and denoted BmOO, BmO1, Bml 0 and Bml 1 for N = 2, a computation of values of path and survivor metrics performed by a block 42, consisting of determining the most probable shift register. For each node of the trellis, a path metric representing the cumulative probability for that node to be part of the transmitted sequence is updated taking into account the path metric calculated in the previous cycle and current branch metric values. This update includes the calculation of two path metrics and the selection of the weakest (surviving path); a storage of the decision bit made by a block 44, in order to restore the decoded signal at the end of the frame by a technique of raising survivors.

Concretely, block 40 calculates the difference between a received value and the possible outputs of the shift register.

Block 42, generally called ACS block (for "Addition, Comparison and Selection") performs at each node of the trellis additions of two metrics of

paths with branch metrics, a comparison of the two obtained path metrics, and a selection of the lowest.

For a calculation on the basis of four possible branch metrics BmOO, BmO1, Bm1O and Bml 1 calculated by block 40, a butterfly operator such as that shown in FIG. 5 can thus be shown for the calculation of the two metrics of following paths: Pmk [t + 1] = VitO = Min (Pmk [t] + BmOO, Pmk + 1 [t] + Bml 0), Pmk + N, a [t + 1] = Viti = Min (Pmk [t] ] + BmOl, Pmk + 1 [t] + Bml 1). Considering that the detection of a minimum by comparison of two values can be performed using a subtractor coupled to a multiplexer, it is noted that this throttle operator requires, to perform the calculations of blocks 40 and 42, namely a calculation of branch metric values and path and survivor metric values of an implementation of the Viterbi algorithm:

for each of the two computations of path and survivor metric values, two add-on hardware modules and one hardware module of

subtraction, four additional subtraction hardware modules for calculating the four branch metric values BmOO, BmOl, Bm10 and Bm11. In all, ten material add / subtract modules are used by this throttle operator, as shown in FIG. 6. If PO and P1 are the two path metrics calculated in the previous cycle, Ref the value received and a, b, c, d the four possible output values, then the butterfly operator 46 illustrated in FIG. 6 comprises at a first sequential level: four subtraction modules 48, 50, 52 and 54 for respectively carrying out b = BmO1, Ref-d = Bm11, Ref-c = Bm10 and Ref-a = BmOO, at a second sequential level: an addition module 56 receiving the output data of the module 54 and the variable PO to realize the operation PO + BmOO, an addition module 58 receiving the output data of the module 52 and the variable P1 to perform the operation P1 + Bm1O, an addition module 62 receiving the output data of the module 48 and the variable PO to perform the operation PO + BmO1, and an addition module 64 received the output data of the module 50 and the variable P1 to perform the operation P1 + Bm11, and at a third sequential level: a subtraction module 60 receiving the output data of the modules 56 and 58 for a comparison of PO + Bm00 and P1 + Bm10 making it possible to deduce the value of VitO, and a subtraction module 66 receiving the output data of the modules 62 and 64 for a comparison of PO + Bm01 and P1 + Bm11 making it possible to deduce the value of Viti . It will be noted that the three addition and subtraction modules 56, 58 and 60 interconnected constitute a third material add / subtract operator 68 and that the three addition and subtraction modules 62, 64 and 66 interconnected between they constitute a fourth material operator of additions / subtractions 70 of identical structure. This identical structure of the third and fourth operators 68 and 70, although having similarities with the structures of the first and second operators 36 and 38 above, differs by the interconnections between the addition and subtraction modules. According to the invention, a generic addition / subtraction material operator of predetermined structure but configurable using at least one parameter is proposed. It appears that the structures of the throttle operator 10 of FFT and of the operator Viterbi 46 imply hardware configurations making it possible to envisage a pooling of their operators 36, 38, 68 and 70, by means of a parameterization of certain modules of addition / subtraction of these operators and links using multiplexers for example. This possible pooling, an example of which is illustrated in FIG. 7, results from the fact that the two aforementioned pairs of operators, the pair of operators 36 and 38 on the one hand for the FFT, the pair of operators 68 and 70 on the other hand for the Viterbi algorithm, comprise an identical distribution of the addition / subtraction modules (2x3) and a systematic connection between one of the modules and the two others of the same operator. It appears more clearly in a common mathematical representation of the respective inputs and outputs of the operators considered. Thus, if we consider the modules 22, 28 and 30 of the first additions / subtractions operator 36, noting El (e) one of the two inputs of the addition module 28, E3 (bd) and E4 ( ac) the two inputs of the subtraction module 22, E6 (e) one of the two inputs of the subtraction module 30, S1 (ac-bd + e) the output of the addition module 28, S2 (ac-bd) the output of the subtraction module 22 and S3 (-ac + bd + e) the output of the subtraction module 30, the following set of relations is obtained: S1 = E1 + S2, S2 = E4 û E3, S3 = E6ûS2. If we now consider the modules 24, 32 and 34 of the second additions / subtractions operator 38, noting El (f) one of the two inputs of the addition module 32, E3 (ad) and E4 (bc ) the two inputs of the addition module 24, E6 (f) one of the two inputs of the subtraction module 34, S1 (ad + bc + f) the output of the addition module 32, S2 (ad + bc) the output of the addition module 24 and S3 (-ad-bc + f) the output of the subtraction module 34, we obtain the following set of relations: S1 = E1 + S2, S2 = E4 + E3, S3 = E6uS2. If we now consider the modules 56, 58 and 60 of the third additions / subtractions operator 68, noting El (Ref-c) and E2 (P1), the two inputs of the addition module 58, E5 (Ref. a) and E6 (P0) the two inputs of the addition module 56, S1 (P1 + Bm10) the output of the addition module 58, S2 (P0 + Bm00- (P1 + Bm10)) the output of the subtraction module 60 and S3 (P0 + Bm00) the output of the addition module 56, the following set of relations is obtained: S1 = E1 + E2, S2 = S3 - S1, S3 = E5 + E6. Finally, if we now consider the modules 62, 64 and 66 of the fourth addition / subtraction operator 70, noting E1 (Ref-d) and E2 (P1) the two inputs of the addition module 64, E5 ( Ref-b) and E6 (P0) the two inputs of the addition module 62, S1 (P1 + Bm11) the output of the addition module 64, S2 (P0 + Bm01- (P1 + Bm11)) the output of the module subtracting 66 and S3 (P0 + Bm01) the output of the addition module 62, we obtain the same set of relations as the previous one.

From these three sets of relations, we can deduce a fourth, common to the four operators mentioned above, with two binary parameters (a and / 3): S1 = E1 + aE2 + (1a) S2, S2 = aS3 + (ù1) eaS1 + (1a) E4 + (ù1) e (1αa) E3, S3 = E6 + aE5ù (1αa) S2. The first operator 36 is obtained with (a, / 3) = (0, 1), the second operator 38 with (a, / 3) = (0, 0) and the third and fourth operators with (a, / 3) = (1, 1).

From this fourth set of relations, it is possible to deduce a common operator comprising at least: a hardware addition module receiving E1 and the output of a multiplexer, controlled according to the value of the parameter a, providing E2 (a = 1) or S2 (a = 0), a material addition / subtraction module (adder for / 3 = 0 and subtractor for / 3 = 1) receiving the output of a first multiplexer, controlled according to the value of the parameter a, supplying S1 (a = 1) 14 or E3 (a = 0), and the output of a second multiplexer, controlled as a function of the value of the parameter a, providing S3 (a = 1) or E4 (a = 0 ), a material addition / subtraction module (adder for a = 0 and subtractor for a = 1) receiving E6 and the output of a multiplexer, controlled according to the value of the parameter a, providing E5 (a = 1) or S2 (a = 0). More advantageously, the generic operator 72 illustrated in FIG. 7 meets these minimum requirements, but also makes it possible to envisage other applications of arithmetic calculations.

It has six input ports E1, E2, E3, E4, E5 and 6 and three output ports S1, S2 and S3. It further comprises a first addition / subtraction module 74 configurable as an adder or subtractor as a function of a parameter / 31 (adder if, 61 = 0 or subtracter si / 31 = 1), receiving El and the output of a first multiplexer 80, controlled according to the value of a parameter a1, providing E2 (a1 = 1) or S2 (a1 = 0), and providing S1. It further comprises a second addition / subtraction module 76 configurable as an adder or subtractor according to a parameter / 32 (adder if / 32 = 0 or subtracter if / 32 = 1), receiving the output of a second multiplexer 82, controlled according to the value of a parameter a2, providing S1 (a2 = 1) or E3 (a2 = 0), and the output of a third multiplexer 84, controlled according to the value of a parameter a3 , providing E4 (a3 = 1) or S3 (a3 = 0), and providing S2. Finally, it further comprises a third addition / subtraction module 78 that can be configured as adder or subtractor as a function of a parameter / 33 (adder si / 33 = 0 or subtracter si / 33 = 1), receiving E6 and the output d a fourth multiplexer 86, controlled according to the value of a parameter a4, providing S2 (a4 = 1) or E5 (a4 = 0), and providing S3. From this we deduce the following set of configurable relations: S1 = El + (ù1) el [a1.E2 + (1ùal) S2], S2 = [(1u3) S3 + a3.E4] + (ù1) e2 e2 [a2. S (1? A2) .E3], S3 = E6 + (ù1) e '[(1α a4) E5 ù a4S2]. By playing on the above-mentioned seven binary parameters (a1, a2, a3, a4, / 31, / 32, / 33), it is possible to obtain not only the configurations of the operators 36, 38, 68 and 70, but also of other configurations that can be used for processing other than the aforementioned FFT and Viterbi calculations.

It should be noted that, in practice, it is necessary to introduce memory elements at the output and / or input of the adders / subtractors to solve the indeterminacy produced by the loopbacks. Thus, as shown in FIG. 8, when (a1, a2, a3, a4, / 31, / 32, / 33) = (0, 0, 1, 1, 0, 1, 1) or (0, 0, 1, 1, 0, 0, 1), the generic operator 72 behaves respectively as the operator 36 or 38. As shown in FIG. 9, when (a1, a2, a3, a4, / 31, / 32, / 33) = (1, 1, 0, 0, 0, 1, 0), the generic operator 72 behaves like the operator 68 or 70. Furthermore, by way of example and as shown in FIG. when (a1, a2, a3, a4, / 31, / 32, / 33) = (1, 0, 1, 0, / 31, / 32, / 33), regardless of the binary values of / 31, / 32, / 33, the generic operator 72 performs several (in this case three) independent addition and / or subtraction operations: E1 +/- E2 = S1, E3 +/- E4 = S2, E5 +/- E6 = S3. Finally, by way of example again and as shown in FIG. 11, when (a1, a2, a3, a4, / 31, / 32, / 33) = (1, 1, 1, 1, / 31, / 32 , / 33), regardless of the binary values of / 31, / 32, / 33, the generic operator 72 performs several (in this case three) cascading addition and / or subtraction operations: [(E1 +/- E2) +/- E4] +/- E6. Note that we find a possible minimal parameterization of the generic operator 72 using the two binary parameters a and / 3 by noting the correlation between the coefficients a1, a2, a3, a4, / 31, / 32 , / 33 in the four minimum configurations required that are the operators 36, 38, 68 and 70. Indeed, in these four configurations, (a1, a2, a3, a4, / 31, / 32, / 33) = (a , a, 1-a, 1-a, 0, / 3, 1-a), with, as previously indicated, (a, / 3) = (0, 1) for the first operator 36, (a, / 3 ) = (0, 0) for the second operator 38 and (a, / 3) = (1, 1) for the third and fourth operators 68 and 70. From the generic operator 72, it is possible to design a data processing processor comprising at least one parameterizable common butterfly operator (using at least the parameters a and / 3) capable of performing a fast Fourier transform calculation in a first configuration and a calculation of values of branch metrics e t values of path and survivor metrics of an implementation of the Viterbi algorithm in a second configuration, by pooling at least one operator such as the operator 72 to perform the functions of the operators 36, 38, 68 and 70.

Thus, while the FFT and Viterbi algorithms are different both in the data they process and in the functions they perform, the pooling of material modules of subtraction and / or addition with the aid of operator such as the operator 72 and the design of a common structure are made possible by the original highlighting of a similarity in operation of butterfly operators that they implement. In terms of hardware complexity, a generic operator such as operator 72 is equivalent to an operator such as any one of operators 36, 38, 68 and 70. Thus, it is possible to confer a "generic" character on a user. data processing processor by implementing the generic operator instead of operators 36, 38, 68 or 70 specific to an FFT or Viterbi algorithm. In addition, the use of this generic operator can result in a gain in complexity by reducing the hardware resources actually implemented. Consider the maximum of butterfly operators required by the current standards and a percentage of each butterfly operator, the latter percentage representing the parallelism rate of the implementation, that is to say the number of operators actually implemented. For a pair of percentages relating to the Viterbi and FFT algorithms, it is possible to calculate the potentially achievable gain by replacing the specific addition / subtraction operators by the aforementioned generic operator in an amount equal to the maximum number of necessary operators. for one or other of the two algorithms. Thus, the genericity of the operator 72 makes it possible to best adapt to the distribution between the number of butterfly operators for the FFT algorithm and that of Viterbi. The gain provided depends on the parallelism of the operators to be replaced. For an increased parallelism of initial Viterbi butterfly operators, the gain will be low (last row of the table). For an increased parallelism of the butterfly operators of the FFT, the gain will be more consequent (last column of the table). Another advantage of the generic operator 72 is to be able to take advantage, in the Viterbi mode, of the fact that the data processed in the FFT mode must be complex and that their real and imaginary parts are in general integer. In Viterbi mode, the processing processor is then able to work with both hard (binary) input data and soft (integer) input data.

Finally, given the variability in the performance of microelectronic technologies, it is advantageous to provide the most regular basic operators / processors possible. Indeed, it is then possible to implement such processors in excess and configure them a posteriori depending on performance or potential failures of each of these processors. Consequently, a processor including at least one generic operator 72 such as that described above is advantageously integrated in a multi-carrier modulating / demodulating telecommunication terminal 88 of the transmitted / received signals and decoding of signals processed by a convolutional code as illustrated in FIG. FIG. 12. The applications of a processing processor including at least one such generic operator and at least two FFT and Viterbi operating modes are multiple whether for a single standard terminal or for a multinorm terminal. Indeed, many standards implement, for example, OFDM modulation (FFT calculation) and require a convolutional code decoding (Viterbi algorithm), among which: DAB digital terrestrial broadcasting, terrestrial digital broadcasting (DVB-T, DVB-H), T-DMB digital terrestrial broadcasting, DRM digital broadcasting, wired links: ADSL, VDSL, Homeplug modem, cable modem (Docsis standard), standards-based wireless networks 802.11a, 802.11g (Wi-Fi), 802.16 (WiMAX) and HiperLAN, Next Generation Mobile Networks (4G). This list is of course not exhaustive since almost all current or studied standards use an OFDM modulation and / or a Viterbi decoding. In addition, recent work has shown that FFT can be applied to more diverse operations than simple modulation. In particular, it can be used for correlation calculations, the genesis of FIR type filters, channel estimation or the detection of several users. Likewise, the Viterbi algorithm has been extended in previous studies to the decoding of Turbos Codes. Thus, the proposed generic operator 72 can be used by a majority of single or multi-standard telecommunication terminal functions. It facilitates their integration by the implementation of homogeneous processing blocks comprising configurable generic operators. Finally, note that the invention is not limited to the embodiment envisaged. It will be apparent to those skilled in the art that various modifications can be made to the embodiment described above, in the light of the teaching that has just been disclosed. In the following claims, the terms used are not to be construed as limiting the claims to the embodiment set forth in this description, but must be interpreted to include all the equivalents that the claims are intended to cover by reason of their formulation and whose prediction is within the reach of the person skilled in the art by applying his general knowledge to the implementation of the teaching which has just been disclosed to him.

Claims (10)

REVENDICATIONS1. A hardware add / subtract operator (72) comprising a plurality of hardware add / subtract modules (74, 76, 78) and a plurality of data links between these modules, on the one hand, and between inputs (E1, E2, E3, E4, E5, E6) and outputs (S1, S2, S3) of the operator and these modules, on the other hand, according to a predetermined structure for carrying out arithmetic calculations, characterized in that at least a portion (74, 76, 78) of the operator addition / subtraction hardware modules and at least a portion (80, 82, 84, 86) of links between these modules are configurable using at least one programmable parameter (a1, a2, a3, a4, / 31, / 32, / 33), at least between a first configuration in which the operator finalizes (72) a calculation of real parts of transform coefficients of Fast Fourier, a second configuration in which the operator finalizes a calculation of imaginary parts of transformer coefficients Fast Fourier RME, and a third configuration in which the operator performs computation of path and survivor metric values of an implementation of the Viterbi algorithm. The add / subtract hardware operator (72) according to claim 1, wherein the add / subtract hardware modules and the configurable links are further configurable using said at least one programmable parameter (a1, a2, a3, a4, / 31, / 32, / 33), in a fourth configuration in which the operator (72) performs several independent addition and / or subtraction operations and a fifth configuration in which the operator finalizes a cascade addition and / or subtraction operations. A hardware add / subtract operator (72) according to claim 1 or 2, comprising a first configurable hardware / add module (74), using a first binary parameter (/ 31), between an adder configuration and a subtractor configuration, a second configurable add / subtract hardware module (76), using a second binary parameter (/ 32), between an adder configuration and a configuration of subtractor, and a third hardware add / subtract module (78) configurable, using a third binary parameter (/ 33), between an adder pattern and a subtractor pattern. A hardware add / subtract operator (72) according to claim 3, comprising: a first link (80) for providing an operand value to the first configurable module (74), using a first multiplexing parameter (a1), between an input data supply configuration (El) of the operator (72) and an output supply configuration (S2) of the second configurable module (76), a second a link (82) for providing a first operand value to the second configurable module (76), using a second multiplexing parameter (a2), between an input data provisioning configuration ( E3) of the operator (72) and an output supply configuration (Si) of the first configurable module (74), a third link (84) for providing a second operand value to the second configurable module (76). ), using a third multiplexing parameter (a3), between a configuration of supply of input data (E4) of the operator (72) and an output supply configuration (S3) of the third configurable module (78), and a fourth link (86) for providing an operand value to the third configurable module ( 78), using a fourth multiplexing parameter (a4), between an input data supply (E6) configuration of the operator (72) and an output supply configuration (S2). ) of the second configurable module (76). The add / subtract hardware operator (72) according to claim 4, wherein each configurable link comprises a multiplexer (80, 82, 84, 86) having two inputs and an output and selecting one of the two inputs using a binary parameter (a1, a2, a3, a4). 25 A digital data processing processor comprising at least one throttle operator (10, 46) including at least one material add / subtract operator (72) according to any of claims 1 to 5, the throttle operator being configurable using said programmable parameter (a1, a2, a3, a4, / 31, / 32, / 33) between a first configuration in which it performs fast Fourier transform computation and a second configuration in which it performs a calculation of branch metric values and path and survivor metric values of an implementation of the Viterbi algorithm. A digital data processor according to claim 6, including a plurality of butterfly operators (10, 46) configurable between said first configuration in which each throttle operator performs said Fast Fourier Transform calculation and said second configuration. wherein each throttle operator performs a calculation of branch metric values and path and survivor metric values of an implementation of the Viterbi algorithm, which throttle operators are structured together for fast Fourier transform calculation by a Cooley-Tukey algorithmic approach in lattice type Radix-2 and for an implementation of the lattice Viterbi algorithm with four reference symbols. A multi-carrier modulating / demodulating telecommunications terminal (136) for transmitting / receiving signals and decoding signals processed by a convolutional code, comprising at least one hardware add / subtract operator (72) according to any one of Claims 1 to 5. 9. Telecommunication terminal (136) according to claim 8, modulation and demodulation OFDM type. 10. Telecommunication terminal (136) according to claim 9, of the multi-standards type, comprising at least one modulator / demodulator with modulation and demodulation OFDM compatible with each implemented standard and at least one signal decoder coded by a convolutional code compatible with each standard implemented.