FR2950173A1 - Direct memory access controller for transferring data to e.g. peripheral, has blocking unit to block reading or writing work pointer if pointer points outside memory space reserved for reading or free memory space reserved for writing - Google Patents

Abstract

The controller (10) has an updation unit formed of management modules (24, 30) and firmware (40) for updating a reading or writing work pointer according to preset update logic. The logic has forward or backward movements of the pointer inside a circular buffer memory (16). A blocking unit formed of the modules and the firmware blocks the work pointer if the reading work pointer points outside a memory space reserved for reading or if the writing work pointer points outside a free memory space for writing defined from a writing pointer to an address preceding a reading pointer. Independent claims are also included for the following: (1) a method of transfer of data from a data source towards a recipient of the data by a direct memory access controller (2) a computer program downloadable from a communication network and/or recorded on a medium readable by a computer and/or executable by a direct memory access controller comprising a set of program code instructions for executing a method of transfer of data from a data source towards a recipient of the data.

Description

The present invention relates to a direct memory access controller, a method for transferring data from at least one data source to at least one recipient of this data implemented by this controller and a corresponding computer program.

Such a controller, qualified as a DMA (English "Direct Memory Access") controller, is generally used in a data processing device CPU such as for example an integrated circuit. It can transfer data processed or provided by the central processing unit from or to a device such as a communication port, a hard disk or any memory, between this device and a local memory of the device for example, without the intervention of the central processing unit except to initiate and conclude the transfer. A DMA controller is for example very useful in a system where repeated access to fast devices could otherwise almost block or at least slow down the processing performed by the central unit. Its presence optimizes the processing time of software applications executed by the central unit by letting the DMA controller handle data transfers to and from the local memory. The invention more particularly applies to a direct memory access controller for transferring data from at least one data source to at least one recipient of this data, via a circular buffer comprising a predetermined number of locations. successive memory elements, each elementary location being identified by an address between a base address and a vertex address of the circular buffer, the access controller including a writes management module adapted to write data received from the source in the circular buffer memory and storage means of a first read pointer and a second write pointer, said read pointer, respectively write pointer, indicating an elementary location of the circular buffer memory in which a piece of data can be read or written respectively.

Such a DMA controller is for example described in the European patent published under the number EP 0 933 926. Its role is to write, in buffers, data which are read successively by recipient decoders having read access to these memories buffer. A write pointer, defined for each buffer, is incremented by an elementary memory location address at each write operation by the DMA controller of a data item in the corresponding buffer memory. Similarly, a read pointer, defined for each buffer memory, is incremented by an elementary memory location address at each read operation by one of the recipients of a data item in the corresponding buffer memory.

Each buffer occupies a memory space between a base address and a vertex address. The write and read pointers of a buffer are then incremented between the base address and the top address of this buffer and return to the base address incrementally after reaching the vertex address. : this is what qualifies these buffers "circular buffers". The advantage of this FIFO type circular buffer configuration (of the English "First ln First Out") is to avoid memory reallocation constraints in case of receiving additional data, since everything happens as if it was possible to write data indefinitely in such a FIFO memory as long as the address to which the write pointer points does not reach that to which the read pointer points, that is to say as long as the memory is not full. But the size of the circular buffer must then be large enough that in normal operation it never fills, which requires to reserve a priori important memory space for this circular memory. A partial solution to this problem is provided by the document EP 0 933 926. When one of the circular buffers is full and the DMA controller writes a data to a location where is stored data not yet read by the recipient concerned, in other words, when the write pointer reaches or exceeds the read pointer of this circular buffer, an error is reported. But this solution is unsatisfactory in most cases, because the initial data corresponding to the rewritten locations are then lost.

In addition, this solution also does not solve the case where one of the recipients tries to read a data while the circular buffer associated with it is empty or the data it stores are obsolete, in others terms when the read pointer reaches or exceeds the write pointer of this circular buffer.

It may thus be desired to provide a direct access controller in memory that makes it possible to overcome the aforementioned problems and constraints. The subject of the invention is therefore a memory direct access controller for transferring data from at least one data source to at least one recipient of this data, via a circular buffer comprising a predetermined number of elementary memory slots. memory, each elementary location being identified by an address between a base address and a top address of the circular buffer, the access controller including a writes management module adapted to write data received from the source in the circular buffer and storage means of a first read pointer and a second write pointer, said read pointer, respectively write pointer, indicating an elementary location of the circular buffer in which a data can be read, respectively written, further comprising a read management module designed to read stored in the circular buffer memory and transfer to the recipient and reading blocking means, respectively write, in the circular buffer according to the relative positions of the elementary locations indicated by said read pointers and writing. Thus, the circular buffer fulfills an intermediate read / write buffer function between the source and the recipient. This function is managed using the read and write pointers by the direct memory access controller which has write and read accesses in this circular buffer. In this way, it is able to synchronize the incoming data stream (s) (flow generated by the source (s)) with the outgoing data stream (s) (flow generated by the recipient or recipients). (s)) without having to synchronize with the central processing unit. Optionally, the storage means further comprise a third read or write pointer, different from the first and second pointers, the controller comprising means for executing update firmware of the third pointer, at each read or write performed by this third pointer, according to a predetermined update logic. By firmware, we mean a software embedded in a hardware component such as an integrated circuit, more precisely in a volatile memory or not of this component. This term is used in the rest of the description as a translation of the English term "firmware".

Thus, it is possible to consider more flexibility in reading or writing data in the circular buffer without the direct memory access controller losing its ability to synchronize incoming and outgoing flows.

Also optionally, the predetermined update logic includes at least one address hop in the circular buffer. Thus, the circular buffer whose memory direct access controller handles the tracking of reads and writes is not used by the controller as a simple FIFO type list. By predetermined programming of the updates of the third write or read pointer according to a predetermined logic comprising at least one address jump, as opposed to a purely incremental logic, it is possible to change the sequence of the data between their reception from the source and their transmission to the recipient via the circular buffer.

Optionally also, the read-blocking means are designed to block any data read in the circular buffer when an update of the first read pointer causes the address to which it points to reach or exceed the address. to which the second write pointer points, and the write-blocking means are arranged to block any writing of data in the circular buffer when an update of the second write pointer causes the address to which it point reaches or exceeds the address to which the first read pointer points. Optionally also, the first read pointer is a memory read-out read pointer for writing data, the third pointer is a read-data read pointer, and the firmware is designed for only read pointers, the write pointer being automatically updated in incrementation without an address jump at each write operation of a data in the circular buffer. In this case, optionally, the direct memory access controller may include means for releasing memory space in the circular buffer memory designed to release, for a data write, a memory space between the location of the old address pointed to and the location preceding that of the new address pointed by the first read pointer, each update of the latter by the execution of the firmware.

Optionally also, the second write pointer is a memory reservation write pointer for writing data, the third pointer is a write pointer, and the firmware is designed for updating. only write pointers, the read pointer being updated automatically by incrementing without an address jump at each operation of reading a data in the circular buffer. In this case, optionally, the direct memory access controller may comprise memory space reservation means in the circular buffer designed to reserve, for a data write, a memory space between the location of the memory buffer. the old address pointed to and the location preceding that of the new address pointed by the second write pointer, each update of the latter by the execution of the firmware. The invention also relates to a method of transferring data from at least one data source to at least one recipient of these data by a direct memory access controller as defined above, such that each data received from the source being sent by the controller to a circular buffer and each piece of data to be transmitted to the recipient being read into the circular buffer by the controller, it includes read-out steps by the controller in the circular buffer and write blocking by the controller in the circular buffer according to the relative positions of the elementary locations indicated by the read and write pointers. Finally, the invention also relates to a computer program downloadable from a communication network and / or recorded on a computer-readable medium and / or executable by a direct memory access controller, comprising code instructions of program for executing the steps of a data transfer method as defined previously when said program is executed by a direct memory controller.

The invention will be better understood with the aid of the following description, given solely by way of example and with reference to the appended drawings in which: FIG. 1 schematically represents the general structure of an access controller 2 shows diagrammatically the general structure of a microprocessor integrated circuit, comprising the direct memory access controller of FIG. 1, FIGS. 3A and 3B represent schematically the structure of a circular buffer managed by the direct memory access controller of FIG. 1, and FIG. 4 illustrates the successive steps of a data transfer method, according to an embodiment of the invention . The direct memory access controller or DMA controller 10 shown in FIG. 1 has the function of transferring data from at least one data source 12 to at least one recipient 14 of these data via a circular buffer 16 having a number predetermined sequence of successive memory locations. The DMA controller 10 is able to access in writing and reading at the elementary locations of the circular buffer memory 16 via a module 18 for controlling the write access and read access data interfaced between the DMA controller 10. and a storage medium incorporating the circular buffer memory 16. It will be noted that in an alternative embodiment, the DMA controller, then carrying the reference 20, includes the storage medium incorporating the circular buffer memory 16 and the access control module 18 in writing and reading. In practice, it may be in the form of an autonomous on-chip system, for example a CMOS-type integrated circuit. As a nonlimiting example of implementation, according to a conceivable architecture called NoC (Network on Chip) or network on chip, the DMA controller 10 or 20 is considered as consisting of functional elements communicating between them via links of a packet-switched network. According to this architecture for carrying out the data transfer from the source 12 to the recipient 14, the DMA controller 10 or 20 comprises the following elements: a link 22 for receiving data from the source 12, a module 24 for managing the data. data writes by the controller 10 or 20 in the circular buffer 16, this module being activated by data it receives from the link 22, a link 26 for sending data to the circular buffer 16 for the writing of these data in elementary memory locations via the write and read access control module 18, a link 28 for receiving data from the circular buffer memory 16 for reading this data in locations elementary memory through the module 18 for controlling write and read access, a module 30 for managing data readings by the controller their 10 or 20 in the circular buffer 16, adapted to receive the data provided by the link 28, and a link 32 for transmitting the data read to the recipient 14. With these elements, the DMA controller 10 or 20 transmits each data received from the source 12 to the circular buffer memory 16, each data to be transmitted to the recipient 14 is then read into the circular buffer memory 16 by the DMA controller 10 or 20. The circular buffer memory 16 thus fulfills a buffer function intermediate between the source 12 and the recipient 14. Optionally, the link 22 for receiving data comprises an input buffer 34 of the FIFO type, for example for temporarily storing data received from the source 12 while the memory circular buffer 16 is write-locked because it is full. Optionally also, the link 32 for transmitting the read data comprises an output buffer 36 of the FIFO type, making it possible, for example, to temporarily store data read in the circular buffer memory 16 while the recipient 14 is not yet ready to receive them or while the output network is temporarily saturated. To synchronize the data flow entering the DMA controller and the outgoing data flow of the DMA controller, the latter also comprises means 38 for storing descriptors of the circular buffer 16. These descriptors comprise at least one basic pointer PB pointing to a base address of the circular buffer 16 in its storage medium, a vertex pointer PS pointing to a vertex address of the circular buffer 16 in its storage medium, a write pointer PE pointing to an elementary location address of the circular buffer 16 where a next data received by the DMA controller 10 or 20 can be written and a read pointer PL pointing to an elementary location address of the circular buffer 16 where a next data can be read to be sent to the recipient.

Since the buffer memory 16 is a circular memory whose size is defined by the number of elementary locations between the base and vertex addresses designated by the PB and PS pointers, each elementary location of this memory to which pointers can point. PE and PL read and write is identified by an address between the base address and the vertex address. The base and vertex pointers PB and PS are predetermined and intended to remain constant while the write pointers PE, respectively read PL, are variable and intended to be updated, for example by incrementing an elementary location in the direction of the base towards the vertex, following a write operation, respectively of reading, in the circular buffer memory. As previously indicated, the circularity of this buffer 16 is related to the fact that when a write or read pointer reaches the vertex address of the memory, incrementing this pointer by one elementary location causes it to point to the base address of the memory.

Therefore, the data temporarily stored in the circular buffer 16 waiting to be read by the DMA controller 10 or 20 to be transmitted to the recipient 14 are located between the address of the read pointer PL and the address preceding that of the PE write pointer in the direction from the base to the top. On the other hand, the memory space in the circular buffer between the address of the write pointer PE and the address preceding that of the read pointer PL in the direction of the base towards the vertex is a free space for the writing. This structure of the circular buffer 16 associated with descriptors PB, PS, PE and PL is illustrated in FIGS. 3A and 3B which will be detailed later.

On the basis of these considerations, the data writes management module 24 is designed to write data, or, on the contrary, block its writing, in the circular buffer memory 16 as a function, in particular, of the values of the write pointers and the PE read pointers. and PL. It is also designed to update the PE write pointer, either automatically using a sequencer by incrementing it by one elementary location, or in a predetermined manner by running a firmware 40 for example stored in the same storage medium as the circular buffer 16. More specifically, in a simple embodiment of the invention, a data to be written in the circular buffer memory 16 must be written to the address indicated by the PE writing pointer; its writing must be blocked if an update of the PE write pointer previously performed by the writing management module 24 makes the address to which it points reaches or exceeds the address to which the reading pointer PL points ( full memory). On the basis of these same considerations, the module 30 for managing data readings is designed to read a data, or on the contrary block its reading, in the circular buffer memory 16 as a function, in particular, of the values of the write and read pointers. PE and PL. It is also designed to update the reading pointer PL, either automatically using a sequencer by incrementing it by one elementary location, or in a predetermined manner by executing a firmware 40 by example stored in the same storage medium as the circular buffer 16. More precisely, in a simple embodiment of the invention, a piece of data to be read in the circular buffer memory 16 must be read at the address indicated by the pointer PL reading; its reading must be blocked if an update of the read pointer PL made previously by the read management module 30 makes the address to which it points reaches or exceeds the address to which the write pointer PE points ( empty memory). Specifically, so that the blocking and unblocking read and write in the circular buffer 16 operate as indicated above, the module 24 for writing management can be programmed to, after each update of the write pointer PE: block any write data in the circular buffer 16 if the write pointer PE reaches the read pointer PL (indication that the memory is full), and unblock the reading of data in the circular buffer 16 if it was blocked and that the write pointer PE again exceeds the read pointer PL. Similarly, the module 30 for managing the readings can be programmed, after each update of the read pointer PL: to block any reading of data in the circular buffer memory 16 if the read pointer PL reaches the write pointer PE (Indication that the memory is empty), and unblock the writing of data in the circular buffer 16 if it was blocked and the read pointer PL again exceeds the write pointer PE. In this way, the writes management module 24 performs a write blocking function when the memory 16 is full and read-free when the empty memory fills up again. The read management module 30 performs a read-lock function when the memory 16 is empty and write-off when the full memory is empty again. The above detailed operation of the write and read management modules 24 and 30 is only one example of implementation of the write and read blocking means in the circular buffer memory 16 using the pointers of FIG. PL and PE read and write, but it will be apparent to those skilled in the art that other implementations or variants are possible to make the circular buffer 16 to read and write blocking according to the value of reading pointers and d PL and PE writing. These features make the DMA controller 10 or 20 capable of synchronizing the incoming data flow from the source 12 and the outgoing stream to the recipient 14. This results in an advantage illustrated in FIG. 2. In this figure, an integrated circuit 50 includes a microprocessor 52, the data source 12 which is for example a local memory for temporary storage of the data processed or used by the microprocessor 52, the recipient 14 which is for example any device or functional operator and the DMA controller according to its variant embodiment including the circular buffer memory 16. All these elements 52, 12, 14 and 20 are interconnected by a conventional data transmission bus 54.

In normal operation of the microprocessor 52 and the DMA controller 20, the microprocessor transfers data to the source 12 (step B), for example in a buffer memory thereof, regardless of the transfers made by the DMA controller between the source 12 and the source 12. the recipient 14 (step C). This is indeed made possible by the synchronization function that can fulfill the DMA controller 20 as described above, thanks to its circular buffer 16 writes and blocking readings. On the other hand, if the DMA controller 20 could not fulfill this function, a conventional request protocol (step A) and acknowledgments (step D) should be implemented between the microprocessor 52 and the DMA controller 20, associated with a data block writing between the microprocessor 52 and the source 12. The transfer of data between the source 12 and the recipient 14 would thus be achieved by the following succession of steps: transmission A by the microprocessor 52 of a transfer request of a block of data to the DMA controller, transmission B of the microprocessor data block 52 to the buffer defined for this purpose in the source 12, transfer C of the data block by the DMA controller from the source 12 to the recipient 14, transmission D by the DMA controller of an acknowledgment to the microprocessor 52 to allow the sending of a new block of data. It therefore clearly appears that the DMA controller 20 as described previously, providing for a synchronization at the level of each data item transferred, makes it possible to simplify the steps of data transfer, in particular by dispensing with steps A and D. In combination with this synchronization function , it is possible, in one embodiment of the invention, to provide a firmware (for example the firmware 40) designed to update at least one of the read and write pointers associated with the circular buffer memory 16 according to a predetermined update logic to add flexibility in reading or writing operations. In this case, in order not to lose the synchronization capacity of the DMA controller 10 or 20, it is necessary to define a new read or write pointer, referred to as a working pointer and bearing the reference PT in FIGS. 3A and 3B. This job pointer is different from the write and read pointers PE and PL defined previously. Like them, it is stored in the storage means 38. It is variable and intended to be updated by the firmware 40 after each read or write operation it performs. In particular, the firmware 40 can be set so that the updating logic of the working pointer PT comprises at least one address jump in the circular buffer 16. By introducing this new pointer PT and the associated firmware 40 which allows for example its displacement by address jumps, forwards or backwards as illustrated in FIG. 3A, in the circular buffer memory 16, the latter of which the DMA controller 10 or 20 manages the tracking of the reads and writes is not used as a simple FIFO type list. It allows the DMA controller 10 or 20 to reorder itself the sequence of data to be transferred between the source 12 and the recipient 14. In a preferred embodiment, the working pointer PT is a read pointer. In this variant, the first read pointer PL is a read pointer with free memory space for writing data. In other words, each time it is updated, the memory space between the location of the old pointed address and the location preceding that of the new address pointed by this first read pointer PL is automatically released for writing. This is because, as previously indicated, the memory space in the circular buffer 16 between the address of the write pointer PE and the address preceding that of the read pointer PL in the direction from the base to the summit is considered in principle as a free space for writing. The working pointer PT is, meanwhile, a read pointer retention of read data. In other words, when data must be read in the circular buffer 16 to be transmitted to the recipient 14, it is read at the address indicated by the working pointer PT, but the update of the working pointer PT after this read does not release the corresponding elementary location for writing. Indeed, the read displacements of the working pointer PT are not necessarily incremental: they are freely predetermined by the firmware 40 in an arbitrary order, preferably between the first read pointer PL and the write pointer PE. According to the applications, a data item read a first time by the working pointer PT can notably be re-read and the data can be read in a different order from that of their storage in the circular buffer memory 16: it is therefore only an update to day of the first read pointer that can free up memory space. For example, in an application for transmitting a video data stream conforming to the MPEG 2 or 4 standard (from the English "Moving Picture Expert Group"), for eight lines of video coefficients stored in the circular buffer memory 16, the Firmware 40 may include instructions for moving the 8x8 macroblock PT work pointer to 8x8 macroblock and in a predetermined order in each macroblock. When all the macroblocks of these eight lines have been read by the working pointer PT, the eight lines of video coefficients are then released in the buffer memory by a microprogrammed update of the first read pointer PL.

It is therefore noted that in this embodiment where the working pointer PT is a read pointer, the firmware 40 includes instructions executed by the read management module 30 for updating the two reading pointers: instructions that may include address jumps forward and / or backward depending on the intended application for the PT work pointer, instructions that may include address jumps, but only ahead and depending on the movements programmed for the pointer PT, for the first read pointer PL. On the other hand, the firmware 40 does not include instructions for updating the write pointer PE, which is for example updated by a sequencer without any address jump and incrementally at each operation. writing a data item in the circular buffer 16. It will also be noted that, as illustrated in FIG. 3A, the movements of the working pointer PT must be programmed so that it points in the zone of the circular buffer memory 16 which comprises actually data to read. If it points, after an update, outside this zone, as illustrated in FIG. 3B, then it can be provided according to the targeted applications, either to generate an error message or to block it. at this position until the PE write pointer catches it.

In a symmetrical embodiment of the previous embodiment, the working pointer PT may be a write pointer. In this second variant, the write pointer PE is a write pointer with reservation of memory space for writing data in the circular buffer memory 16. In other words, whenever it is set to day, the memory space between the location of the old dotted address and the location preceding that of the new address pointed by this write pointer PE is automatically reserved for writing. The working pointer PT is, meanwhile, an effective writing pointer write data in any predetermined order in the memory space reserved by the pointer PE. In other words, when data must be written in the circular buffer 16, it is at the address indicated by the working pointer PT, the update of which does not necessarily obey an incremental logic. Its movements are freely predetermined by the firmware 40 in an arbitrary order in the reserved memory space.

It is therefore noted that in this second embodiment where the working pointer PT is a write pointer, the firmware 40 includes instructions executed by the writing management module 24 for updating the two write pointers. : instructions that may include forward and / or backward address jumps depending on the intended application for the PT work pointer, instructions that may include address jumps, but only forward and depending on the trips programmed to the PT work pointer, for the PE write pointer. On the other hand, the firmware 40 does not include instructions for updating the read pointer PL, which is, for example, updated by a sequencer without an address jump and incrementally at each read operation of the read pointer. a data in the circular buffer memory 16. An example of a data transfer method that can be implemented by the DMA controller 10 or 20 will now be detailed, in the context of the first aforementioned alternative embodiment, in which the pointer PT is a read pointer to retention of read data. The successive steps of this method are illustrated in FIG. 4. During a first step 100, the controller 10 or 20 is waiting for an instruction to read or write data in the circular buffer 16 This step 100 is followed by a write triggering step 102, on the instruction to write a piece of data in the circular buffer memory 16. During this write triggering step, the writing management module 24 is activated. . As a non-limiting exemplary embodiment, it extracts storage means 28 the value of a first descriptor indicating whether the writing in the circular buffer memory 16 is blocked or not. Then, during a test step 104, according to the value of this first descriptor, it is decided to continue or not to write the data considered. If the first descriptor indicates that the writing is blocked, we go back to step 100, otherwise we go to a step 106.

In step 106, the writes management module 24 retrieves storage means 28 the address to which the write pointer PE points. It then executes the writing of the data considered in the corresponding elementary location.

Then, during an updating step 108, the address pointed by the write pointer PE is incremented by one elementary location in the circular buffer memory 16. Finally, during a step 110, the module 24 writes management means 28 retrieves the address to which the first read pointer points PL and then eventually updates the value of the first write blocking descriptor and that of a second descriptor blocking readings, in the following situations: if after the update of step 108, the address pointed by the write pointer PE reaches that pointed by the first read pointer PL (indication that the memory 16 is full), modification of the first descriptor for the latter to indicate a blocking writes, if after the update of step 108, the address pointed by the writing pointer PE differs from that pointed by the first pointer PL reading while the sec The descriptor indicates a blocking of the readings, the modification of the second descriptor for the latter indicates an authorization of the readings. Step 110 is followed by a return to step 100. Step 100 is also followed by a read triggering step 112, on the instruction to read a piece of data in the circular buffer memory 16. During this step read trigger, the read management module 30 is activated. As a non-limiting exemplary embodiment, it extracts from the storage means 28 the value of the second descriptor indicating whether the reading in the circular buffer memory 16 is blocked or not. Then, during a test step 114, the read management module 30 determines whether the recipient 14 is ready to receive the data considered. This test can be done in many ways. If the DMA controller 10 or 20 has the output buffer 36, then it can be considered that a data transfer can be performed as long as this output buffer 36 is not full. Otherwise, a conventional communication protocol may provide that the recipient 14 informs the DMA controller 10 or 20 of its ability to receive data by messages in the predetermined format. If the transfer of the data to the recipient 14 is not possible, we go back to step 100, otherwise we go to another test step 116. During this test step 116, depending on the value of the second descriptor, it is decided to continue or not to read the data considered. If the second descriptor indicates that the reading is blocked, we go back to step 100, otherwise we go to a reading step 118. In this step 118, the read management module 30 extracts storage means 28 the address to which the PT work pointer points. It then executes the reading of the data considered in the corresponding elementary location. Then, during an updating step 120, the address pointed by the working pointer PT is updated, either forwards or backwards, by one or more elementary locations, by the module 30 for managing the readings according to the instructions of the firmware 40. If this is also provided for by the instructions of the firmware 40, the first read pointer PL can be updated also at this step, forward and from one or more elementary locations. Finally, during a step 122, the read management module 30 possibly updates the value of the first write blocking descriptor and that of the second read blocking descriptor, in the following situations: if after the update in step 120, the address pointed to by the first read pointer PL reaches that pointed by the write pointer PE (indication that the memory 16 is empty), modifying the second descriptor so that the latter indicates a blocking of the readings if, after the updating of step 120, the address pointed by the first read pointer PL differs from that pointed by the write pointer PE, while the first descriptor indicates a blocking of the writes, modification of the first descriptor for the latter to indicate an authorization of the entries.

Step 122 is followed by a return to step 100. It is clear that the previously described direct memory access controller and its operation for the data transfer not only make it unnecessary to synchronize a microprocessor and the controller associated with it, but also to add flexibility in the transfer of data, especially when the data sequence desired by the recipient is not the same as that provided by the source. This is for example a useful property in applications for processing and transferring image or video data in the context of MPEG standards. It will also be noted that the invention is not limited to the embodiments envisaged. In particular, in the foregoing, to simplify the description it has been envisaged an application where the transfer is made from a single source to a single recipient, but the principle of the invention applies in the same way with several sources and / or several recipients. Similarly, a direct memory access controller according to the invention can manage several circular buffers and therefore several sets of descriptors (pointers, blocking descriptors, etc.) associated. More generally, it will be apparent to those skilled in the art that various modifications may be made to the embodiments described above, in light of the teaching just disclosed. In the following claims, the terms used are not to be construed as limiting the claims to the embodiments set forth in this specification, but should be interpreted to include all the equivalents that the claims are intended to cover because of their formulation and whose prediction is within the reach of the person skilled in the art by applying his general knowledge to the implementation of the teaching which has just been disclosed to him.

Claims (10)

REVENDICATIONS1. A direct memory access controller (10, 20) for transferring data from at least one data source (12) to at least one recipient (14) thereof via a circular buffer (16) comprising a number predetermined location of successive memory locations, each elementary location being identified by an address between a base address and a vertex address of the circular buffer, the access controller including a scripting module (24) adapted to write data received from the source (12) into the circular buffer (16) and means (38) for storing a first read pointer (PL) and a second write pointer (PE) , said reading pointer, respectively of writing, indicating an elementary location of the circular buffer in which data can be read, respectively written, characterized in that it further comprises a module ( 30) for reading data stored in the circular buffer (16) and transferring them to the recipient (14) and means (24, 30, 40) for reading, respectively write-locking, in the circular buffer (16) according to the relative positions of the elementary locations indicated by said read and write pointers. The direct memory access controller (10, 20) according to claim 1, wherein the storage means (38) further comprises a third read / write pointer (PT) different from the first and second pointers. , the controller comprising means (24, 30) for executing a firmware (40) for updating the third pointer (PT), at each reading or writing performed by this third pointer (PT), according to a logic of predetermined update. The direct memory access controller (10, 20) of claim 2, wherein the predetermined update logic includes at least one address hop in the circular buffer. A direct memory access controller (10, 20) as claimed in claim 2 or 3, wherein the read-blocking means (30, 40) is adapted to block any reading of data in the circular buffer (16) when an update of the first read pointer (PL) causes the address to which it points to reach or exceed the address to which the second write pointer (PE) points, and in which the blocking means write (24, 40) are adapted to block any write of data in the circular buffer (16) when an update of the second write pointer (PE) causes the address to which it is pointing to reach or exceed address to which the first read pointer (PL) points. The direct memory access controller (10, 20) according to any one of claims 2 to 4, wherein the first read pointer (PL) is a memory space clear read pointer for writing of the data, the third pointer (PT) is a read-read read pointer, and wherein the firmware (40) is designed for updating only the read pointers (PL, PT), the pointer of writing (PE) being updated automatically by incrementing without an address jump at each write operation of a piece of data in the circular buffer (16). A direct memory access controller (10, 20) according to claim 5, comprising means (30) for releasing memory space in the circular buffer memory (16) arranged to release, for data writing, a memory space between the location of the old dotted address and the location preceding that of the new address pointed to by the first read pointer (PL), each update of the latter by the execution of the firmware (40). ). The direct memory access controller (10, 20) according to any one of claims 2 to 4, wherein the second write pointer (PE) is a memory reservation write pointer for the memory. writing, the third pointer (PT) is a write pointer, and wherein the firmware (40) is designed for updating only the write pointers (PE, PT), the read pointer ( PL) being automatically updated incrementally without an address jump at each read operation of a data in the circular buffer (16). A direct memory access controller (10, 20) according to claim 7, including means (24) for reserving memory space in the circular buffer memory (16) adapted to reserve, for a data write, a memory space between the location of the old dotted address and the location preceding that of the new address pointed to by the second write pointer (PE), each update of the latter by the execution of the firmware ( 40). A method of transferring data from at least one data source (12) to at least one recipient (14) of such data by a direct memory access controller (10, 20) according to any of claims 1 at 8, characterized in that each data received from the source (12) is transmitted (106) by the controller (10, 20) to a circular buffer memory (16) and each data item to be transmitted to the recipient (14) is read (118) in the circular buffer (16) by the controller (10, 20), it comprises steps (110, 122) for reading block by the controller in the circular buffer and write-lock by the controller in the circular buffer according to the relative positions of the elementary locations indicated by the read and write pointers. Computer program downloadable from a communication network and / or recorded on a computer readable medium and / or executable by a direct memory access controller (10, 20), characterized in that it comprises instructions program code for executing the steps of a data transfer method according to claim 9 when said program is executed by a direct memory access controller.