FR2945393B1 - Procede de protection de circuits electroniques, dispositif et systeme mettant en oeuvre le procede - Google Patents
Procede de protection de circuits electroniques, dispositif et systeme mettant en oeuvre le procedeInfo
- Publication number
- FR2945393B1 FR2945393B1 FR0902225A FR0902225A FR2945393B1 FR 2945393 B1 FR2945393 B1 FR 2945393B1 FR 0902225 A FR0902225 A FR 0902225A FR 0902225 A FR0902225 A FR 0902225A FR 2945393 B1 FR2945393 B1 FR 2945393B1
- Authority
- FR
- France
- Prior art keywords
- electronic circuits
- system implementing
- protecting electronic
- protecting
- implementing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0902225A FR2945393B1 (fr) | 2009-05-07 | 2009-05-07 | Procede de protection de circuits electroniques, dispositif et systeme mettant en oeuvre le procede |
PCT/EP2010/056072 WO2010128068A1 (fr) | 2009-05-07 | 2010-05-05 | Procede de protection de circuits electroniques, dispositif et systeme mettant en œuvre le procede |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0902225A FR2945393B1 (fr) | 2009-05-07 | 2009-05-07 | Procede de protection de circuits electroniques, dispositif et systeme mettant en oeuvre le procede |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2945393A1 FR2945393A1 (fr) | 2010-11-12 |
FR2945393B1 true FR2945393B1 (fr) | 2015-09-25 |
Family
ID=41625197
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0902225A Expired - Fee Related FR2945393B1 (fr) | 2009-05-07 | 2009-05-07 | Procede de protection de circuits electroniques, dispositif et systeme mettant en oeuvre le procede |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2945393B1 (fr) |
WO (1) | WO2010128068A1 (fr) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8738843B2 (en) * | 2010-12-20 | 2014-05-27 | Lsi Corporation | Data manipulation during memory backup |
US9043642B2 (en) * | 2010-12-20 | 2015-05-26 | Avago Technologies General IP Singapore) Pte Ltd | Data manipulation on power fail |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6961890B2 (en) * | 2001-08-16 | 2005-11-01 | Hewlett-Packard Development Company, L.P. | Dynamic variable-length error correction code |
US7210077B2 (en) * | 2004-01-29 | 2007-04-24 | Hewlett-Packard Development Company, L.P. | System and method for configuring a solid-state storage device with error correction coding |
US8402325B2 (en) * | 2004-08-02 | 2013-03-19 | St-Ericsson Sa | Data storage and replay apparatus |
US8171380B2 (en) * | 2006-10-10 | 2012-05-01 | Marvell World Trade Ltd. | Adaptive systems and methods for storing and retrieving data to and from memory cells |
US8122323B2 (en) * | 2007-03-08 | 2012-02-21 | Intel Corporation | Method, apparatus, and system for dynamic ECC code rate adjustment |
-
2009
- 2009-05-07 FR FR0902225A patent/FR2945393B1/fr not_active Expired - Fee Related
-
2010
- 2010-05-05 WO PCT/EP2010/056072 patent/WO2010128068A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2010128068A1 (fr) | 2010-11-11 |
FR2945393A1 (fr) | 2010-11-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 7 |
|
PLFP | Fee payment |
Year of fee payment: 8 |
|
PLFP | Fee payment |
Year of fee payment: 9 |
|
PLFP | Fee payment |
Year of fee payment: 10 |
|
PLFP | Fee payment |
Year of fee payment: 11 |
|
ST | Notification of lapse |
Effective date: 20210105 |