FR2936626A1 - DEVICE FOR PARALLEL PROCESSING OF A DATA STREAM - Google Patents

Abstract

The present invention relates to a data stream processing device comprising K calculation tiles (TC) and interconnection means (4) for transferring the data stream between the calculation tiles (TC). According to the invention, each calculation tile (TC) comprises: - a storage unit (UM) making it possible to format the data of the stream, - one or more control units (UC) making it possible to provide instructions for carrying out a processing on the data, - at least one processing unit (UT) per control unit (CU), the processing units (UT) carrying out the instructions received from the control units (CU), - an input / output unit (UES) for routing the data stream between the interconnection means (4) and the storage unit (UM) on the one hand, and between the processing units (UT) and the means (4) of interconnection on the other hand. The invention allows a great modularity in the processing of data flow while limiting the consumption of electrical energy.

Description

The invention relates to a device for processing a data stream. It is located in the field of computational architectures and finds particular utility in embedded multimedia type applications incorporating a video sensor. These include mobile telephony, mobile media players, cameras and digital camcorders. The invention is also useful in telecommunications applications and, more generally, in any signal processing chain processing high speed digital data. Signal processing in general, and image processing in particular, require significant computing power, especially in recent years with the rapid increase in resolution of image sensors. In the field of embedded applications intended for the general public, strong constraints in terms of manufacturing cost are added to the power consumption constraints (of the order of a few hundred milliwatts). To meet these constraints, image processing is commonly performed from dedicated computing modules operating in data flow mode. The "data flow" mode, commonly called "data flow" in the English literature, is understood as a data processing mode according to which the data entering the calculation module are processed as and when the rate of their arrival, a result being provided at the output of the calculation module at the same rate, possibly after a latency time. The dedicated calculation modules make it possible to respect manufacturing cost constraints because of their small silicon surface and the performance constraints, in particular as regards computing power and electrical consumption. However, such modules suffer from a problem of flexibility, the supported processing can not be modified after the realization of the modules. At best, these modules are configurable. Otherwise, 30 says, a number of process related parameters may be modified after completion. One solution to this lack of flexibility is to use fully programmable processors. The most commonly used processors are the signal processing processors, well known in the English literature under the acronym "DSP" for "Digital Signal Processor". Disadvantages of these processors are their large silicon footprint and their power consumption making them often unsuitable for embedded applications very constraints. Compromises between dedicated computing modules and fully programmable processors are currently under development. According to a first compromise, a circuit comprises a unit for processing very long instruction word data, called a VLIW unit for "Very Long Instruction Word", and a unit for executing an instruction on several calculation units, called SIMD unit for "Single Instruction Multiple Data". In some current embodiments, VLIW and / or SIMD type calculation units are installed in the circuit as a function of the computing power required. The choice of the type of unit to be included in the circuit, their number and their chaining is decided before the realization of the circuit by an analysis of the application code and the necessary resources. The order in which the units are chained is fixed and it does not allow to change thereafter the sequence of treatments. In addition, the units are generally quite complex because the control code of the application is not separated from the processing code. Thus, the processing operators of these units are large, which leads to an architecture whose silicon surface and power consumption are greater at equal computing power. According to a second compromise, a code in C language can be transformed into a set of elementary instructions by a specific compiler. The set of instructions is then implemented on a configurable matrix of predefined operators. This technology can be compared to that of the user programmable gate array, better known by the English acronym FPGA for "Field Programmable Gate Array", the computation grain being larger. It therefore does not allow to obtain programmable circuits, but only configurable circuits by compiling the code. If it is desired to integrate program code portions not initially planned, then computing resources that are not present in the circuit are required. It becomes difficult or impossible to implement this code.

An object of the invention is in particular to overcome the aforementioned drawbacks by proposing a calculation structure that is programmable while limiting the power consumption. To this end, the subject of the invention is a device for processing a data stream comprising K calculation tiles and interconnection means for transferring the data stream between the calculation tiles. Each calculation tile comprises: Io - a storage unit for formatting the data of the stream, - one or more control units for providing instructions for processing on the formatted data, at least one unit of data. processing by control unit, the 15 processing units carrying out the instructions received from the control units, - an input / output unit for routing the data stream between the interconnection means and the storage unit of on the one hand, and between the processing unit (s) and the interconnection means on the other hand. The invention has several advantages. A first advantage is the possibility of modifying the code to be executed by the processing units, even after completion of the circuit supporting the device. A second advantage is the possibility of carrying out, in parallel, either identical processing on several data of the stream, or more complex processes for the same number of clock cycles, taking advantage of the paralleling of the processing units. A third advantage is the possibility of producing a chain of devices according to the invention in order to perform other processing on the data stream. A fourth advantage is that the code to be executed by the processing units comprises only calculation instructions but no control or address calculation instructions.

The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given by way of example, a description given with regard to the appended drawings which represent: FIG. 1, an example of processing device of a data stream according to the invention, - Figure 2, an example of a processing unit comprising a processor with very long instruction words, - Figure 3, an example of management of a block FIG. 4 is an exemplary management of a block of neighborhood registers in a case where the data of the block of formatting memories are in order, FIG. an example of management of the neighborhood register block in the case where the data of the formatting memory block are not in order, - FIG. 6, a set of timing diagrams illustrating the temporal management of a block of neighborhood registers, - Figure 7, an exemplary embodiment a calculation tile comprising a plurality of parallel processing units. FIG. 8, a set of timing diagrams illustrating the time management of a storage unit for a calculation tile comprising two parallel processing units; FIG. 9, an embodiment of an input unit; FIG. 10, an exemplary implementation of the device according to the invention for video images, FIG. 11, a schematic representation of a Bayer filter, FIG. 12, an exemplary embodiment of FIG. an insertion operator. The following description is made in connection with a processing chain of a video data stream from a video sensor such as a CMOS sensor. The processing chain makes it possible, for example, to reconstruct color images from a monochrome video sensor on which a color filter, for example a Bayer filter, is applied, to improve the quality of the images rendered, or to realize morphological operations such as erosion / dilatation or low-level processing pixels of advanced applications such as image stabilization, red-eye correction or face detection. However, the device according to the invention may equally well be suitable for processing a data stream other than those originating from a video sensor. In particular, the device can process a stream of audio data or data in the Fourier space.

FIG. 1 diagrammatically represents a device 1 for processing a data stream according to the invention. A video sensor 2 generates a digital data stream directed to the processing device 1, via a data bus 3. The data from the video sensor 2 is referred to as raw data. Device 1 processes this raw data 15 to output data qualified as final data. For this purpose, the device 1 according to the invention comprises processing units UT, control units UC, storage units UM and input / output units UES grouped into K calculation tiles TC. The device 1 also comprises interconnection means 4 such as data buses 41, 42. These interconnection means 4 make it possible to transfer the flow of data between the different calculation tiles TC. Each calculation tile TC comprises a storage unit UM, one or more control units UC, at least one processing unit UT per control unit UC and an input / output unit UES. The storage units UM make it possible to format the data of the stream so that it can be processed by the processing units UT according to code instructions issued by the control units UC. The input / output units UES make it possible to route the data stream between the interconnection means 4 and the storage units UM on the one hand, and between the processing units UT and the interconnection means 4 on the other hand. 'somewhere else. In the example of FIG. 1, the device 1 comprises 4 calculation tiles TC, the first and the fourth calculation tiles TC1 and TC4 each comprising a storage unit UM, a control unit UC, a processing unit UT, and an input / output unit UES, the second calculation tile TC2 comprising a storage unit UM, a control unit UC, two processing units UT and an input / output unit UES, and the third calculation tile TC3 comprising a storage unit UM, two control units UC, two processing units UT per control unit UC and an input / output unit UES. Each calculation tile TC makes it possible to perform a function or a series of functions from code instructions. As part of a video processing chain, each calculation tile TC performs for example one of the following functions: correction of the white balance, demosaicing, noise reduction, sharpening of the outlines. The composition of a calculation tile TC depends in particular on the function or functions it has to perform. In particular, the number of control units UC composing a calculation tile TC depends on the number of different treatments to be performed simultaneously by the calculation tile TC. Each control unit UC within the calculation tile TC may include its own code, a calculation tile TC comprises for example as many UC control units as 15 separate processing to be performed in parallel on the data.

The UT processing units can be more or less complex. In particular, they may comprise either simple dedicated operators, for example composed of logic blocks, or processors. Each UT processing unit is independent of the others and may have different operators or processors. Dedicated operators are for example multipliers, adders / subtracters, assignment operators or shift operators. Advantageously, the processing units UT contain only the 25 dedicated operators commonly used for the treatment envisaged. A processing unit UT may also include a processor. In a first embodiment, the processor comprises a single arithmetic and logical unit. In a second embodiment, the processor is a very long word processor, commonly referred to as VLIW processor for "Very Long Instruction Word". Such a processor may comprise several arithmetic and logical units. In a preferred variant, a VLIW processor comprises, for example instruction decoders, no longer arithmetic and logical units but only calculation operators, a local memory and data registers. Advantageously, only the computation operators necessary for the execution of the computation codes to be produced are implanted in the processor during its design. Then two or more of them can be used in the same cycle to perform separate operations in parallel. Unused operators do not receive clock signals. The power consumption of the UT processing units is thereby reduced. These advantageous characteristics have led to a particular embodiment, shown in FIG. 2. In this figure, the VLIW processor comprises two channels. In other words, it can execute up to two instructions in the same clock cycle. The processor comprises a first instruction decoder 21, a second instruction decoder 22, a first set of multiplexers 23, a set of calculation operators 24, a second set of multiplexers 25, a set of data registers 26 and local memory 27. The instruction decoders 21 and 22 receive instructions from a control unit UC. According to the instructions received, the multiplexers 23 direct data to be processed on an input of one of the calculation operators 24 and the multiplexers 25 direct the processed data to the data registers 26. The data registers 26 containing the processed data can be connected to processor outputs. The size of the very long instructions is, for example, 48 bits, ie 24 bits per channel. Calculation operators 24 thus work in 24-bit precision. In the context of a video processing and more particularly an image reconstruction from data from a video sensor, the calculation operators 24 are advantageously two adders / subtracters, a multiplier, an assignment operator , a write operator in the local memory and an offset operator. Still according to a particular embodiment, the execution of the instructions may be conditioned by a positioning of a flag. The instruction can then be supplemented by a prefix indicating the execution condition. The flag is for example a bit of a register containing the result of an instruction executed during the preceding clock cycle. This bit may correspond to the zero, sign or carry indicators of the register. At each instruction, the instruction decoders 21 and 22 test the positioning of the flag associated with this instruction. If this positioning conforms to the execution condition, the operation is executed, otherwise it is replaced by a non-operation instruction, called NOP. At the end of the cycle of each instruction, the flag value is sent to the two instruction decoders 21 and 22 in order to test the possible condition of a next instruction. According to a particular embodiment, each instruction word is coded on 24 bits. The first 3 bits (bits 0 to 2) can contain the instruction condition, the next two bits (bits 3 and 4) can encode the data access mode, the sixth, seventh, and eighth Io bits (bits 5). to 7) can encode the identifier of the operation, the next four bits (bits 8 to 11) can designate the destination register, the next four bits (bits 12 to 15) can designate the source register and the last 8 bits (bits 16 to 23) can contain a constant. An example of programming using such a coding is given in the appendix. The device 1 for processing a data stream comprises M control units UC, M being between 1 and N, where N is the number of processing units UT. In the case where the number M of control units UC is equal to the number N of processing units UT, each processing unit UT may have its own control unit UC. In the case where the number M of control units UC is smaller than the number N of processing units UT, then at least one calculation tile TC comprises several processing units UT, as in the example of FIG. TC2, TC3). A control unit UC of this calculation tile TC then provides instructions to a plurality of processing units UT, these processing units UT being said in parallel. A control unit UC may include a memory for storing the code instructions for the processing unit (s) UT that it serves. A control unit UC may also include an ordinal counter, an instruction decoder and an address manager. In the context of a raw image processing obtained by a color filter, the address manager and the ordinal counter make it possible to apply a different treatment according to the color of the current pixel. In particular, the code may be divided into code segments, each code segment including instructions for one of the colors of the filter. The address manager may indicate to the ordinal counter the color of the current pixel, for example red, green or blue. According to a particular embodiment, the address manager comprises a two-bit word for encoding up to four colors or different types of pixels in a pixel neighborhood of size two by two. At each clock cycle, the ordinal counter is incremented by an offset value depending on the value of the word. The ordinal counter then makes it possible to point to the segment of code corresponding to the color of the current pixel. The four offset values are determined at the compilation of the code io according to the number of instructions of each of the code segments. The use of an address manager and an ordinal counter makes it possible to unload the programmer and thus avoids that he himself determines programmatically the nature of the current pixel. This management becomes automatic and allows a shorter execution time and simpler programming. In the particular case where the processed images are monochrome, the same instructions are applied to all the pixels. The offset values are then equal and determined so that the ordinal counter points to the first instruction after the initialization code.

The device 1 for processing a data stream also comprises K storage units UM, K being between 1 and M. A calculation tile TC may comprise several control units UC, as in the example of FIG. (TC3). The same data of the flow, or neighboring data, present in the storage unit UM can then be processed differently by the processing unit UT of the calculation tile, each control unit UC providing instructions to at least one unit UT treatment. The main function of the storage units UM is to format the data of the flow in order to facilitate the access of the processing units UT to these data. Specifically, the UM storage units format the data as neighborhoods and manage access to the data when UT processing units are in parallel. According to a first embodiment, the storage units UM each comprise a number of data registers equal to the number of processing units UT located in the calculation tile TC of the storage unit UM considered. According to a second embodiment, which is particularly suitable for processing video images, the storage units UM each comprise a first memory block called a shaping memory block and a second memory block called a neighborhood register block. Since the storage units UM are independent of each other, the data stream processing device 1 can comprise both storage units UM according to the first embodiment and storage units UM according to the second embodiment. The second embodiment allows processing on data neighborhoods. For a video image, a neighborhood can be defined as a mesh of adjacent pixels, this mesh being generally square or at least rectangular. A rectangular mesh may be defined by its dimension VlxVc where VI is the number of pixels of the neighborhood along the lines and Vc is the number of pixels of the neighborhood according to the columns. The block of formatting memories stores the data of the stream so that it can be copied systematically at each arrival of a new datum. The neighborhood register block allows access to the pixels of the current neighborhood by the processing unit (s) UT of the considered calculation tile. FIG. 3 illustrates, by a block 31 of formatting memories represented at different time steps T, an example of management of the block 31 for data corresponding to a stream of pixel values coming from a video sensor 32. 32 video sensor is Nc resolution columns by NI lines. The resolution is for example VGA (640x480), "HD Ready" (1080x720) or "Full HD" (1920x1080). Pixels are sent and stored as they arrive at block 31 of formatting memories. This block 31 is of dimension NcxVI. In other words, the block 31 comprises NcxVl memory cells arranged in a mesh of Nc columns and VI lines. Common values for VI are three, four, five, six, or seven. Physically, block 31 may consist of one or more memory modules. Block 31 can be managed as a shift register. In other words, at each time step or clock cycle, the data is shifted to make room for the new incoming data.

Advantageously, the block 31 is managed as a conventional memory so that the pixels are copied in their order of arrival. In the latter case and in a first embodiment, a CPT counter is considered incrementing to each incoming data item. Each new pixel coming from the data stream is then copied into a cell 33 of the formatting memory block 31 located on the line corresponding to E (CPT / Nc), where E (x) is the function returning the integer part of a number x, and the column corresponding to the rest of CPT / Nc. The counter CPT is reset every time it reaches the value equal to NcxVI. In a second embodiment, a CPTC counter is considered to increment after each incoming data and a counter CPTL is incremented each time the counter CPTC reaches the value Nc. The counter CPTC is reset each time it reaches the value Nc and the counter CPTL is reset every time it reaches the value VI. Each new pixel from the data stream is then copied into cell 33 whose line number corresponds to the value CPTL. and whose column number corresponds to the CPTC value. FIG. 4 illustrates an exemplary management of the neighborhood register block for data from the block 31 of formatting memories. The block 34 of neighborhood registers comprises a number of neighborhood registers equal to VlxVc. These neighborhood registers are arranged in the same way as the neighborhood of pixels, that is to say that they form a mesh of VI lines and Vc columns of registers. The copy of the data from the block 31 of the formatting memories to the neighborhood registers 25 begins as soon as there is a number of data in the block 31 equal to Ncx (VI-1) +1. In the case of a neighborhood of dimension 3x3, represented in FIG. 4, the copying of the data thus begins when two lines of data plus one piece of data are present in block 31. In one embodiment, the data is copied to each clock cycle by groups of VI data 30 of the same column. At a given time step, the number of the column to be copied is given by the value of CPTC. This column indeed comprises the last pixel arrived in block 31. Advantageously, a column 35 of VI data registers is added to the neighborhood registers. This column 35 makes it possible to block the accesses to the registers of the block 34 by the processing units UT only during a single clock cycle, that of the shifting of the values in the block 34. Otherwise, the accesses are blocked both during the offset of the values and during the copying of the data from the block 31. During a first clock cycle, the data of the column of the block 31 indicated by the counter CPTC are copied in the registers of the column 35. During a second clock cycle, all data in block 34 and column 35 are shifted by one column. Thus, for a neighborhood of dimension 3x3, in the same clock cycle, the data of a first column 341 are shifted to a second column 342, while the data of this column 342 is shifted to a third column 343 and that the data of the column 35 are shifted to the column 341. Because of the cyclic management of the block 31, the data are not always stored in the block 31 in the order of the lines of the video sensor 32. In this case, the pixels must be copied in column 35 or, if appropriate, in column 341 of block 34, in a different order. FIG. 5 illustrates such a case where the last data of the stream are stored on the first line of block 31. In the case of a neighborhood of dimension 3 × 3, the copying of the pixels in column 35 can be managed by the steps of FIG. following placement: the last arriving pixel always goes to the third line 347 of the neighborhood register column 35; if the counter CPTL is equal to zero, in other words if the last pixel has arrived at the first line 311 of the block 31, then the pixel of the second line 312 of the block 31 is copied to the first row 345 of the column 35, where the pixel of the third line 313 of the block 31 is copied to the second line 346 of the column 35; if the counter CPTL is equal to one, in other words if the last pixel has arrived at the second line 312 of the block 31, then 30 o the pixel of the first line of the block 31 is copied to the second line 346 of the column 35, the pixel of the third line 313 of the block 31 is copied to the first line 345 of the column 35; if the counter CPTL is equal to two, in other words if the last pixel has arrived at the third line 313 of the block 31, then the pixel of the first line 311 of the block 31 is copied to the first line 345 of the column 35 the pixel of the second line 312 of the block 31 is copied to the second line 346 of the column 35.

More generally, in the case of a neighborhood of size VcxVI, the pixel of the block 31 formatting memories located line NoLigne and the column indicated by CPTC is recopied in particular in column 35, or, where appropriate in the first column 341 of block 34, at the line defined by (CPTL + NoLine + 1) modulo VI. According to a particular embodiment, the copying of the pixels of the block 31 in the register column 35 is not performed simultaneously with the offset of the pixels in the block 34. This embodiment allows the processing units UT to access the data present in block 34 of neighborhood registers for a longer period. Figure 6 shows a set of timing diagrams for implementing this embodiment. The temporal offset between the copying of the pixels and the offset of the pixels in the block 34 can be achieved by introducing, in addition to a first clock, called the pixel clock 61 and allowing to clock the data flow and the copying of the pixels, a second clock, called the offset pixel clock 62. This offset pixel clock 62 may be at the same frequency as the pixel clock 61 but shifted in time. This offset corresponds, for example, to a period of the clock of the UT processing units 63. The data present in the block 34 are then accessible during the entire period separating two clock ticks from the offset pixel clock 62. access to the neighborhood registers by the processing units UT can be achieved by an input / output port, for example integrated to each processing unit UT, whose number of connections is equal to the number of neighborhood registers multiplied by the size Datas. Each neighborhood register is connected to the input / output port. Advantageously, each storage unit UM comprises a multiplexer whose number of inputs is equal to the number of neighborhood registers of the block 34 and the number of outputs is equal to the number of data that can be processed simultaneously by the processing unit UT of the TC calculation tile considered. The processing unit UT may then comprise an input / output port whose number of connections is equal to the number of data that can be processed simultaneously multiplied by the size of the data. In this case, a processing unit UT comprising a two-way VLIW processor processing 12-bit data may comprise an input / output port with 24 (2x12) connections.

According to a particular embodiment, the same storage unit UM provides data to several processing units UT in parallel. This embodiment is possible thanks to the storage units UM comprising a block 31 of formatting memories and a block 34 of neighborhood registers. FIG. 7 illustrates an example of a calculation tile TC where a storage unit UM provides data with n processing units UT in parallel, n being less than or equal to the number N of processing units UT of the device 1. The instructions are supplied to the n processing units UT by a control unit UC. According to this embodiment, the block 34 of neighborhood registers has dimension (n + Vl-1) xVl. In other words, the block 34 comprises (n + Vl-1) xVl data registers arranged in a mesh of n + Vl-1 columns and VI lines. For example, for three parallel UT processing units and a 5x5-sized neighborhood, a cell of 7 (= 3 + 5-1) columns and 5 rows of registers is required. In addition, a column 35 of VI data registers can be added to block 34. Thus, access to the neighborhood registers by the processing units UT is blocked only during a single cycle of the processing units UT. The copy of the data from block 31 to register column 35 then begins when block 31 of formatting memories has Ncx (Tv-1) +1 data. Furthermore, for n UT processing units 25 in parallel, the data processing is performed when n new data has arrived in block 31. The access to the neighborhood registers by the n processing units UT can also be performed by a user. Integrated input / output port to each UT processing unit. The number of connections of the input / output port of each processing unit UT is then equal to the number of neighborhood registers to which the processing unit UT requires access multiplied by the size of the data. Similarly, the storage unit UM may comprise a multiplexer whose number of inputs is equal to the number of neighborhood registers of the block 34 and the number of outputs is equal to the number of data that can be processed simultaneously by the n units. UT processing unit, each UT processing unit comprising an input / output port whose number of connections is equal to the number of data that can be processed simultaneously by said processing unit UT multiplied by the size of the data. FIG. 8 illustrates, by a set of timing diagrams, an example of management of a calculation tile TC comprising two processing units UT in parallel. A first timing diagram 81 represents the clock of the processing units UT of cadence Farchi. A second timing diagram 82 represents the clock pixel clock Fp1Xe ,. The pixel clock sets the rate at which the stream data arrives, which is sent to the block 31 of formatting memories. The rate Farchi can be equal to pxFp1xe1 with p a positive integer. According to FIG. 8, the rate Fp1Xe is four times higher than the rate Farchi • Each processing unit UT thus has four clock cycles per data to be processed. A third timing diagram 83 represents an offset clock. This clock generates two successive clock ticks 831, 832 after every other clock pulse of the pixel clock. At each clock stroke of the shift clock, the data of block 34 is shifted by one column. A fourth timing diagram 84 represents the offset pixel clock. The rate of this clock is substantially equal to half the clock rate, a clock stroke 840 being generated after the two clock ticks 831, 832 of the shift clock. In general, the rate of the offset pixel clock is equal to 1 / n times the Foxe rate of the pixel clock. At each clock stroke 840 of the offset pixel clock, the data is copied from block 31 to block 35. Access to neighborhood registers by UT processing units is possible between two clock ticks 840. the offset pixel clock.

According to a particular embodiment, the interconnection means 4 comprise a number Nb_bus of data bus. 30 Nb_bus can be defined by the following relation: Nb_bus = Kx (Fp, Xei / Farchi) +1. This embodiment makes it possible to connect the K calculation tiles TC to each other by performing a spatiotemporal multiplexing whose time division multiplexing ratio Mux_t is defined by the relation: MUX t = Farchi / Fpixel • The Mux_t temporal multiplexing ratio allows define an equal number of time slots, the read and write access permissions can be set for each time interval. For example, for a rate Fp1Xe, equal to 50 MHz and a 200 MHz Farchi rate, the four calculation tiles TC of FIG. 1 can be linked in any order if the interconnection means 4 comprise at least two (4x (50/200) +1) data bus, the calculation tiles TC being addressed by a time multiplexing of ratio four (= 200/50). According to this embodiment, each UES input / output unit can handle the read and write access permissions according to the bus number Nb_bus and the time division multiplex Mux_t report. In particular, each UES input / output unit may comprise registers for determining the time intervals during which the calculation tile CT considered has a read or write access authorization on one of the data buses. and, for each of these time slots, the data bus for which read or write access is allowed. For example, an input / output unit UES comprises, for the management of write access permissions, Nb_bus registers of size log2 (Mux_t) bits, where log2 (x) is the function returning the logarithm in base 2 of the number x and, for the management of the read access authorizations, a register of size log2 (Nb_bus) bits specifying the number of the bus to be read and a register of size log2 (Mux_t) bits specifying the time interval. An exemplary embodiment of such an input / output unit UES is shown in FIG. 9. The input / output unit UES comprises two registers 91 and 92 of 2 bits each, the register 91 managing the authorization write access on the bus 41 and the register 92 managing the write access authorization on the bus 42. The contents of the registers 91 and 92 are compared with the value of the current time interval, for example by comparators 93 and 94 and, in case of equality, the writing of data is allowed on the bus 41 or 42 concerned. The input / output unit UES also includes a 1-bit register 95 specifying the number of bus 41 or 42 to be read and a 2-bit register 96 specifying the time interval for reading. The contents of the register 96 are also compared to the current time interval, for example by a comparator 97 and, in the case of equality, the reading of the data is authorized on the bus 41 or 42 concerned. This embodiment has the advantage that each UES input / output unit individually manages the access permissions between the calculation tiles TC and the buses 41 and 42. Therefore, no centralized control unit is needed. . The value of the registers of each input / output unit UES is set at the start of the system according to the desired chaining of the calculation tiles TC. An unused CT calculation tile may have the values of the registers of its input / output unit UES initialized so as to have no read or write rights on the bus 41 or 42.

According to a particular embodiment, represented in FIG. 1, each calculation tile TC further comprises a series block BS comprising as many data registers as UT processing units present in the tile considered, the size of the registers being at least equal to the size of the data in the stream. The serial block BS of a calculation tile TC receives as input data from the processing unit or units UT 15 and is outputted to the input / output unit UES. During write authorization on one of the buses 41 or 42, the data present in the serial block (BS) are sent sequentially on this bus 41 or 42.

FIG. 10 illustrates an exemplary implementation of the device 1 for processing a data stream for processing operations to be performed on raw images. The raw images are for example derived from a Bayer filter 110, for example represented in FIG. 11. With such a filter, a color image is constituted by a mosaic of pixels of red, green and blue colors. In particular, the mosaic consists of an alternation of 25 blue and green pixels on a first type of line and an alternation of green and red pixels on a second type of line, the types of lines also being alternated so as to form diagonals of green pixels. The device 1 according to the invention is particularly suitable for such data. Indeed, for each type of line, it is possible to constitute a calculation tile TC capable of simultaneously processing several pixels although they are of different color. In one embodiment, shown in FIG. 10, the calculation tile TC comprises, on the one hand, a first control unit UC1 supplying a first code to a first and a second processing unit UT1 and UT3 and, d secondly, a second UC2 control unit providing a second code to a second and a fourth processing unit UT2 and UT4. The first code is specific to a first pixel color, for example red, and the second code is specific to a second pixel color, for example green. The code can also be divided into code segments, an address manager then indicating to the control units UC1 and UC2 the color of the processed pixel. The processing units UT1, UT2, UT3 and UT4 then act on the data present in the block 34 of neighborhood registers according to the instructions they receive. In this case, the first and third processing units UT1 and UT3 act on red pixels and the second and fourth processing units UT2 and UT4 act on the green pixels. The calculation tile thus makes it possible to process simultaneously, but distinctly, four pixels of the block 34 of neighborhood registers. In the case of the Bayer filter 110, two control units UC1 and UC2 per line suffice because a line has only two different colors. Of course, the calculation tiles can be adapted according to the applied color filter.

According to a particular embodiment, the interconnection means 4 are able to transfer data whose size is greater than that of the data of the stream. The device 1 according to the invention may then include an insertion operator for concatenating each data flow with a complementary data. Fig. 12 shows such an insertion operator 120. The insertion operator 120 comprises an input bus 121 connected to an input of an insertion block 122 whose output is connected to an output bus 123 The insertion operator 120 may also include a memory 124 for storing the complementary data. The memory 124 is linked to the insertion block 122 to allow the transfer of the complementary data. The size of this data must be less than or equal to the difference between the maximum size of the data that can be transferred by the interconnection means 4 and the size of the data of the stream. The size of the input bus 121 must be adapted to the size of the data of the stream while the size of the output bus 123 must be adapted to the size of the stream data concatenated with the complementary data. The complementary data may be dissociated from the data of the stream, for example by offsets, and used by calculation tiles TC to perform a specific processing on the data of the stream. In the context of a video image processing, the complementary data item contains, for example, a value representative of a noise or gain correction to be applied to the pixels. The same correction can thus be applied to all the pixels of the image. The insertion operator can be inserted on one of the buses 41, 42 of data, for example between the video sensor 2 and the calculation tiles TC or between two calculation tiles TC. In one embodiment, the insertion operator 120 is made by a calculation tile TC. The calculation tile TC then comprises a storage unit UM containing the complementary data and a processing unit UT making it possible to concatenate the data of the stream with the complementary data item. The additional data is for example stored in a data register of the storage unit. This embodiment has the advantage of avoiding the insertion of an additional component into the data flow processing chain. It is made possible thanks to the modularity of the device 1 according to the invention. 20 APPENDIX Instruction set (on 48 bits: 24 bits per channel) Composition of the instruction word on 24 bits: 0..2 -> 3 bits Condition; 3..4 -> 2 bits Data access mode 5 .. 7 -> 3 bits Operation identifier 8..11 -> 4 bits Register Destination 12..15 -> 4 bits Register Source 10 16 ..23 -> 8 bits of constant Execution if flag = 1 Execution if flag = 0 Update of the flag on Carry Update of the flag on Result at ZERO Update of the flag on Sign (1 if> 0, 0 if <0)

Postfix of the instructions: 20 Allows to choose the source r (D, A, B): R [D] register destination; R [A] source register, R [B] source register c (D, A, C): R [D] destination register; R [A] source register, C Constant v (D, A, V): R [D] destination register; R [A] source register, Neighbor [V] If the 8 bits of argument B are formed as follows: "10 ... 0 <V>" instead of "0 .. <V>" 25 on will take as neighbor the value stored by the register V is Neighbor [R [V]] m (D, A, M): R [D] destination register; R [A] source register, M address memory of local memory

Use: 30 The VLIW Allows to work on two channels OPi (Dm ...) / OPj (Dn) It is necessary however that j! = I and that m! = N Except in the case of complementary conditional instructions: F_OP; No operation if FLAG = 1 35 NF_OP; No operation if FLAG = 0 One can thus write on the same line F__OP (Dm ...) / NF_OP (Dn ...) Since whatever the value of Flag, only one will be actually executed

40 List of operations - NOP PREFIX: F_ NF_NOP F_NOP 45 NF NOP - LD PREFIX: F _ NF fZ_ fC fS_ LDr (D, A): R [D] = R [A] LDc (D, C): R [ D] = C; C signed constant 50 LDv (D, V): R [D] = Vois [V] LDv (D, V); R [D] = See [R [V]] LDm (D, M); R [D] = SP [M]

- ADD; SUB; MUL 55 PREFIX: F NF fZ fC_ fS Prefix instructions: F: NF: fc _ JZ JS Two signed adders are available, so ADDO and ADDI can be used simultaneously without restriction on the channel. PREFIX: ## STR5 ## (R, D, A, B): R [D] = R [A] + R [B] ADDOc (D, A, C): R [D] = R [A] + C ; C constant signed ADDOv (D, A, V): R [D] = R [A] + See [V] ADDOv (D, A, -V); R [D] = R [A] + See [R [V]] ADDOm (D, A, M); R [D] = R [A] + SP [M] IDEM for ADDO, SUBO SUBI, and MUL; all these operations are signed

- SHIFT PREFIX: F_NN fZ_ fC _ fS A signed shift operator is used to shift the values to the right or to the left according to the sign of the offset An offset of 0 equates to a SHIFTc assignment (D, A, C): if (C > O) R [D] = R [A] C if (C <O) R [D] = R [A] C - INV 25 I.TVr (D, A) R [D] = -R [A] IVVc (D, C) R [D] = -C I_NVv (D, V) R [D] = -Vis [V] INVv (D, -V): R [D] = -Vol [R [V]] INVm (D, M): R [D] = -SP [M] 30 Program code example This code performs the following operation: For a 2x2 neighborhood, sets RI to the average of the neighboring pixels and sets RO to 255 if the value of the average is> 128; increments R2 if the pixel is 255 (to have the pixel count> 128 at the end of processing)

1 #include "macros.h" 2 .initcode 3 LDc (R0, 0); / NOP 40 4 LDc (R1, 0); / NOP 5 LDc (R2, O); / NOP 6 LDc (R3.0); / NOP 7 LDc (R4, O); / NOP 8 LDc (R5, O); / NOP 45 9 NOP / NOP 10 .pixel code 0 11 LDv (R1, VO) / NOP 12 LDv (R2, V1) / ADDOv (R1, R1, V0) ADDOv (R2, R2, V2) / ADD1 (R1 , R1, V3) 50 14 ADDO (R1, R1, R2) / NOP SHIFTc (R1, R1, -2) / NOP 16 fS SUBc (R7, R1, 128) / NOP 17 F _LDc (R0, O) / NF LDc (R0, 255); in this exceptional case we can call 2x LD since one is executed and the other is not executed. 18 NF ADDOv (R2, R2,1) / NOP 19 NOP / NOP 1520 20 .pixelcodel 21 .pixelcode2 22 .pixelcode3 We could write taking full advantage of the two VLIW channels: .pixelcode0 11 LDv (R1, V0) / NF ADDOv (R2, R2, 1) 12 LDv (R2, V1) / ADDOv (R1, R1, VO) 13 ADDOv (R2, R2, V2) / ADD1 (R1, R1, V3) ADDO (R1, R1, R2)! NOP SHIFTc (R1, R1, -2) / NOP 16 fS SUBc (R7, R1, 128) / NOP 17 F LDc (R0, O) / NF LDc (R0, 255)

Claims (17)

REVENDICATIONS1. Device for processing a data stream, characterized in that it comprises K calculation tiles (TC) and interconnection means (4) for transferring the data flow between the calculation tiles (TC), each tile calculation system (TC) comprising: - a storage unit (UM) for formatting the flow data, - one or more control units (UC) for providing instructions for processing on the formatted data. - at least one processing unit (UT) per control unit io (CPU), the processing units (UT) carrying out the instructions received from the control units (UC), - an input / output unit (UES) for routing the data stream between the interconnection means (4) and the storage unit (UM) on the one hand, and between the processing unit (s) (UT) and the means (4) 15 d interconnection on the other hand. 2. Device according to claim 1, characterized in that control units (UC) each comprise a mer- dior in which a program is stored, the program being able to be divided into code segments, each code segment comprising different instructions for to allow a different treatment of the flow data according to their nature. 3. Device according to claim 2, characterized in that the data stream 25 comes from a video sensor (2) delivering images of Nc columns by NI lines of pixels, each image comprising an alternation of two types of lines, each type of line comprising two types of pixels, at least one calculation tile (TC) comprising two control units (UC), the program of each control unit (CU) being divided into four code segments, each code segment corresponding to the different types of pixels to take into account. 4. Device according to claim 3, characterized in that the pixel type depends on its color. 5. Device according to any one of the preceding claims, characterized in that storage units (UM) each comprise a number of data registers equal to the number of processing units (UT) of the calculation tile (TC). considered. 6. Device according to any one of claims 1 to 4, characterized in that the data stream comes from a video sensor (2) delivering images of Nc columns by NI rows of pixels, memory units (UM ) each comprising a block (31) of NcxVl size formatting memories and a block of neighboring VlxVc neighborhood registers (34), where VI is the number of pixels along the lines and Vc is the number of pixels following the lines. columns of a neighborhood. 15 7. Device according to claim 6, characterized in that the block (34) of neighborhood registers further comprises a column (35) of VI data registers. 8. Device according to any one of claims 6 or 7, characterized in that calculation tiles (TC) each comprise a storage unit (UM), a control unit (UC) and n processing units (UT). ), the storage unit (UM) supplying data to the n processing units (UT) and the control unit (UC) providing instructions to the n processing units (UT), the block (34) of Neighborhood comprising (n + Vl-1) xVl data registers arranged in a mesh of n + Vl-1 columns and VI lines. 9. Device according to any one of claims 6 to 8, characterized in that it comprises a CPTC counter and a CPTL counter, the counter CPTC incrementing after each incoming data and being reset each time that it reaches the value Nc, the counter CPTL is incremented each time the counter CPTC reaches the value Nc and is reset to zero each time it reaches the value VI, the incoming data being stored in a cell (33) of the block (31) of formatting memories whose line number corresponds to the value CPTL and whose column number corresponds to the value CPTC. 10. Device according to claims 7 and 9, characterized in that the data column of the block (31) formatting memories marked by the CPTC value is copied, at each clock stroke of the data stream, in the column (35) of VI data registers and then shifted to a first column (341) of the neighborhood register block (34). io 11. Device according to claim 10, characterized in that each datum of the block (31) shaping memories located in the column marked by the CPTC value and the line marked by NoLigne is copied in the column (35) of VI data registers in the line marked with (CPTL + NoLine + 1) modulo VI, where NoLine takes all positive integer values between 1 and VI. 12. Device according to any one of the preceding claims, characterized in that the interconnection means (4) comprise a number Nb_bus of data bus (41, 42) defined by the relation: Nb_bus = KX (Fp, xeI / Farchi) +1, where Fp1Xe, is a frequency of the data flow and Farci is a frequency of operation of the processing units (UT), the Farchi frequency being equal to pxFp1Xe, with p a positive integer. 25 Device according to claim 12, characterized in that input / output units (UES) each comprise Nb_bus registers of log2 (Mux_t) bits size to manage the write access permissions, a register of size log2 (Nb_bus ) bits and a register of size log2 (Mux_t) bits for the management of read access authorizations, Mux_t being defined by the relation Mux_t = Farchi / FpixeI. 14. Device according to claim 13, characterized in that the calculation tiles (TC) are addressed by a time division multiplexing whose ratio is defined by the relation: MUX_t = Farchi / Fpixel • 15. Device according to any one of the preceding claims, characterized in that calculation tiles (TC) each comprise a series block (BS) comprising a number of data registers equal to the number of processing units (UT) of the calculation tile (TC) considered, each serial block (BS) of a calculation tile (TC) receiving as input data from the processing units (UT) of the calculation tile (TC) considered and being connected in output to the input / output unit (UES) of said calculation tile (TC). 16. Device according to any one of the preceding claims, characterized in that processing units (UT) each comprise a processor comprising two instruction decoders (21, 22), a first set of multiplexers (23), calculation operators (24), a second set of multiplexers (25), data registers (26) and a local memory (27), the instruction decoders (21, 22) receiving instructions from a unit control unit (UC), the first set of multiplexers (23) directing the data to be processed on an input of one of the calculation operators (24), the second set of multiplexers (25) directing the processed data to the registers of the data (26) and the processor being able to execute up to two instructions per clock cycle of the processor. 25 17. Device according to any one of the preceding claims, characterized in that it comprises an insertion operator (120) for concatenating data flow with a complementary data, computing tiles (TC) being able to dissociate the flow data of the complementary data so that the processing units (UT) of said calculation tiles (TC) perform instructions on the flow data as a function of the complementary data.